Editing Acorn Archimedes A5000 (section)

== Architecture ==

The A5000 utilized a refined architecture combining proven components with cost-effective design choices. The ARM3 processor provided the performance foundation, while careful system integration minimized component count and manufacturing costs.

=== System Design ===

{| class="wikitable styled-table" style="width:70%; text-align:center;"
! Component !! Implementation !! Function
|-
| ARM3 || 25 MHz, 4 KB cache || Central processor
|-
| MEMC1a || Single chip || Memory controller, DMA
|-
| VIDC1a/VIDC20 || Enhanced timing || Video and sound
|-
| IOC || Standard implementation || I/O control, timers
|-
| COMBO chip || 82C711 || IDE, floppy, serial, parallel
|}

The integration of multiple I/O functions into the 82C711 COMBO chip reduced board complexity and cost. This chip handled IDE and floppy disk control, serial and parallel ports, and real-time clock functions, eliminating several discrete components used in earlier designs.

=== Memory Architecture ===

The A5000's memory system balanced performance with cost:

{| class="wikitable styled-table" style="width:85%; text-align:center;"
! Configuration !! SIMM Type !! Slots Used !! Total RAM !! Expansion Path
|-
| 2 MB model || 2× 1MB 30-pin || 2 of 4 || 2 MB || Add 2 SIMMs
|-
| 4 MB model || 4× 1MB 30-pin || 4 of 4 || 4 MB || Replace all
|-
| 8 MB upgrade || 4× 2MB 30-pin || 4 of 4 || 8 MB || Maximum
|}

The use of industry-standard 30-pin SIMMs reduced memory costs compared to proprietary modules. The MEMC1a controller supported up to 8 MB directly, though RISC OS could only utilize 8 MB total including VRAM.