Editing IBM RS/6000 (section)

== CPU Families ==

{| class="wikitable styled-table" style="width:100%; text-align:center;"
|+'''RS/6000 CPU implementations'''
! CPU !! Implementation !! Years !! RS/6000 use
|-
| POWER1 (RIOS) || 7–9 chip MCM || 1990– || 7012-320 / 340; 7013-520 / 530 / 540 / 550; 7015-930 / 950
|-
| POWER1 (RSC) || Single chip || 1992– || 7011-220 / 230
|-
| POWER2 || 8-chip MCM, CMOS-5 || Sep 1993– || 7012-380 / 390 / 39H; 7013-58H / 580 / 590 / 591; 7015-R10 / R20 / R24
|-
| P2SC (POWER2 Super Chip) || Single die, CMOS-6S, 15 M transistors || Oct 1996– || 7012-397 (160 MHz); 7013-595 (135 MHz)
|-
| PowerPC 601 || Single chip, 0.6 µm CMOS || Sep 1993– || 7011-250 (66 MHz); 7020 / 7007-N40 notebook (50 MHz)
|-
| PowerPC 604 || Single chip || 1995– || 7248-100 (100 MHz)
|-
| PowerPC 604e || Single chip || 1996– || 7043-140 / 150; 7025-F30 / F40 / F50; 7248-120 / 133
|-
| IBM POWER3 || 64-bit, CMOS 7S || 1998– || 7043-260 (200 MHz)
|-
| POWER3-II || 64-bit, CMOS 7S copper interconnect || 1999– || 7044-170 / 270 (333 / 375 / 450 MHz)
|-
| RS64-II "Northstar" || 64-bit, CMOS 6S || 1998– || 7026-H50 (340 MHz)
|-
| RS64-III "Pulsar" || 64-bit, CMOS 7S copper || 1999– || 7025-F80; 7026-H70 / H80 (450 / 500 MHz)
|}

The MCM-based POWER1 and POWER2 use one large ceramic module with several dies for the integer unit, floating-point unit, instruction cache, data cache, and storage control. The P2SC of 1996 collapses the POWER2 MCM into a single die.<ref>http://ps-2.kev009.com/jasper/ibm/RS6K.arch.html</ref><ref>https://ardent-tool.com/RS6000/ENUS197-267.pdf</ref>

<gallery widths="220" heights="160" mode="packed">
File:IBM PowerPC 601 die.jpg|PowerPC 601 — 7011-250 and N40 notebook
File:IBM PowerPC 604e die.jpg|PowerPC 604e — 7043-140 / 150, 7025-F50, 7248-120 / 133
</gallery>