Editing Jump-less Dual-Kernal Switcher (section)

== Design overview ==
{| class="wikitable" style="width:70%; text-align:center;"
! colspan="3" | Major functional blocks (SKS64 reference design)
|-
| style="width:33%;" | '''EPROM / Flash'''<br />27C256 (4 × 8 KB)<br />27C512 (8 × 8 KB)<br />27C010 (16 × 8 KB)
| style="width:33%;" | '''ATtiny13A μC'''<br />Decodes reset / RESTORE pulses,<br />latches two address bits to pick the bank
| style="width:33%;" | '''74xx logic'''<br />HCT08 & HCT02 gate ROM CS<br />and isolate the bus during bank switch
|-
| colspan="3" | The board plugs into the KERNAL socket (U4 on long-boards, U4/U32 on 250469) and '''requires no cuts or flying leads'''.
|}

The micro-controller runs at 9.6 MHz (internal RC) and samples '''~60 Hz VSYNC''' from the VIC-II to time-out key-presses reliably over PAL & NTSC.  Two GPIO lines drive A15/A16 of the EPROM through 10 k pull-ups, giving up to 4/8/16 selectable images depending on device size.

=== Switch-less selection methods ===
* '''Short double-reset''' – press the C64 reset button twice within < 0.9 s.  
* '''Long RESTORE hold''' – hold the RESTORE key ≥ 1 s while tapping RUN/STOP.  
The μC counts either event and advances an internal bank counter; the chosen bank number is flashed back on the C64 power LED (1-long, 2-long, …).  A cold-reset is then issued.