Editing Psion Series 3 (section)

=== Why the Series 3 is slower ===

The clock is held to 3.84 MHz for a specific, documented reason. '''ASIC1 assembles each 16-bit word from two 8-bit ROM reads''', which needs ROM with about a 250 ns access time at that clock. Readily available mask ROMs of the period managed 200 ns, and that is what capped the Series 3.<ref name="sibo">Psion PLC, ''SIBO Hardware Reference'', version 2.10, 3 February 1995, in the [https://doc.psion.info/books/the-psion-sibo-software-development-kit/page/hardware-reference Psion Documentation Project]. Source for the SIBO architecture, ASIC1 and ASIC2 functions, the clock-speed limitation, the memory and I/O decoding, the interrupt table, the watchdog, the NMI sources, the timekeeping mechanism and the supply rails.</ref>

The [[Psion Series 3a|3a]]'s ASIC9 does 16-bit accesses instead, which doubled the clock for the same ROM.<ref name="sibo" />