Editing Psion Series 3a (section)

=== ASIC9 ===

The Series 3 and its MC and HC siblings used three chips — the V30H, '''ASIC1''' (the system controller, about 4300 gates in a 100-pin flat pack) and '''ASIC2''' (the clock, keyboard, buzzer, SSD and power-supply interface, about 2200 gates in an 80-pin flat pack). '''ASIC9 integrates all three.'''<ref name="sibo" />

That integration bought several things that matter when you are working on a 3a:<ref name="sibo" />

* '''Double the clock speed.''' The Series 3 was held to 3.84 MHz because ASIC1 assembled each 16-bit word from two 8-bit ROM reads, needing about 250 ns ROM. ASIC9 does 16-bit accesses, so the same 200 ns mask ROM supports 7.68 MHz.
* '''Bank-switched memory beyond the V30H's 1 MB limit''', through four page registers PSEL0–PSEL3, giving a 16 MB RAM space and a 16 MB ROM space.
* '''A hardware 32-bit real-time clock''' clocked at 1 Hz. On the earlier ASIC1/ASIC2 machines the CPU had to wake periodically to keep time, and '''if it could not start — no main batteries — the time was lost'''. The 3a keeps time independently.
* '''Hardware wait on pack access''', which stops the CPU clock automatically when the serial controller is busy instead of polling for it.
* '''Switch-on from the membrane key pads''', not just the on key.
* '''Improved grey scale''': the second video map became an attribute map that dims only set pixels.