Editing Sega CD (Model 2) (section)

== Hardware Architecture ==
{| class="wikitable" style="width:70%; text-align:center;"
|+'''Major ICs (VA0 main-board)'''
! Part !! Function(s)
|-
| '''MC68EC000''' (64-pin) || Primary 16-bit CPU @ 12.5 MHz
|-
| '''315-5880 “MCD ASIC 2”''' || Sub-CPU bus arbiter • Word-RAM controller • rotation / scaling / 3×3 matrix
|-
| '''315-5788''' || OKI MSM6295-compatible DMA + CD-SUB code ROM
|-
| '''Ricoh RF5C164''' || 8-channel PCM generator, 10-bit DAC
|-
| '''CXD2510Q''' || CD-DSP / decoder – replaces discrete CN-303 & CXP controllers in Model 1
|-
| '''315-5684-B''' || RGB DAC + stereo mixer (shares with Genesis 2)
|}

Internally, software sees '''identical registers''' to Model 1; all games and dev tools remain compatible.

=== Clock Scheme (NTSC) ===
* Master XTAL = '''12.500 MHz × 4 = 50.000 MHz''' → ÷4 = 12.5 MHz (68k)  
* Z80 (in Genesis) still sourced from 53.693 MHz ÷15 ≈ 3.58 MHz  
* Word-RAM dual-ported clock = 25 MHz.

=== Memory Map (MC68EC000) ===
{| class="wikitable" style="width:70%;"
|+'''Sega CD Model 2 Physical Address Space'''
! Range !! Size !! Device
|-
| $0000 00–$0FFF FF || 1 MB || Program RAM
|-
| $0200 00–$03FF FF || 2 MB || Word-RAM (dual-bank 0/1)
|-
| $0400 00–$05FF FF || 2 MB || PRG-RAM mirror / save RAM (battery)  
|-
| $0600 00–$07FF FF || 2 MB || PCM sample RAM mirror
|-
| $0800 00–$0BFF FF || 4 MB || BIOS ROM (128 KB mirrored)  
|-
| $0C00 00–$0DFF FF || 2 MB || CD-DSP & sub-CPU registers  
|-
| $0E00 00–$0E00 FF || 256 B || Gate array I/O (gate, LEDs, reset)
|}