Editing SuperCPU and Turbo Accelerators (section)

== Technical principles ==

; Bus arbitration  
The VIC-II still needs '''40 CPU cycles per raster line''' for video-DMA.  Turbo accelerators therefore:
* '''Stretch φ2 low-time''' (Turbo Master/Flash 8) so that fast code runs only when the VIC is idle.
* '''Shadow RAM''' on-board and replay writes to the real C-64 DRAM during idle slots (SuperCPU).  
  A fast 16-bit 65816 runs from zero-wait SRAM while the VIC keeps reading the slow motherboard RAM.

; Memory mapping  
Most units expose extra RAM through the standard '''\$FFxx banking lines''' (EXROM/GAME or REU registers).  The SuperCPU’s *SuperRAMCard* appears at \$DF00 and can be logically mapped in 64 KB pages, giving GEOS 2.0 a full 4–16 MB workspace.

; Compatibility layers  
* '''IO shadowing''' – writes to \$D000–\$DFFF are mirrored so that timers/sprites still update at 1 MHz cadence.  
* '''KERNAL patch''' – accelerators supply a tiny ROM that intercepts IRQ entry/exit to resynchronise with VIC safe-lines (Turbo Master).  
* '''Turbo OFF switch''' – most devices fall back to 1 MHz for cycle-exact demos or $DD00 colour‐cycle loading schemes.