Editing IBM PALM processor (section)

=== Dutchess Masterslice Gate Arrays ===

The 13 gate arrays on the PALM board are IBM's '''"Dutchess"''' masterslice — an uncommitted-logic-array (ULA) family fabricated by IBM at its bipolar facility (most likely IBM East Fishkill, New York, though this is not explicitly stated in published sources for PALM specifically).

Dutchess specifications:

{| class="wikitable styled-table" style="width:100%;"
|+'''IBM Dutchess masterslice gate array'''
! Parameter !! Value
|-
| Logic family || Bipolar, Schottky-TTL-compatible
|-
| Supply voltage || +5 V
|-
| Gate count per array || ~134 logic gates
|-
| Internal logic mix || 60 × three-input NAND + 40 × four-input NAND + 34 × two-input NOR off-chip drivers
|-
| Propagation delay || ≈ 10 ns per gate
|-
| Package || Square metal can with leadframe
|-
| Personalisation || Metal mask (final aluminum interconnect layer) — the same wafer can be cut into different logic functions by changing only the metal layers
|}

A '''masterslice''' (also known as a sea-of-gates ULA in later terminology) is a wafer pre-fabricated with a fixed array of unconnected transistors. The specific logic function of each chip is set by the metal interconnect layers added at the end of fabrication — this lets IBM build 13 different gate-array functions on the PALM board from the same underlying silicon.

Dutchess was IBM's bipolar workhorse masterslice family for small-system controllers in the early 1970s and predates the larger IBM ECL families used in System/370 mainframes.

[[File:IBM 5100 overhead view.jpg|right|thumb|320px|IBM 5100 chassis interior — the PALM card mounts on the A1 backplane alongside ROS, RWS and I/O cards. The PALM card carries 13 bipolar gate arrays in metal cans on a single multi-layer PCB. Image: Wikimedia Commons, public domain.]]