Editing Diagnostic Serial Console (section)

== Memory Architecture and Address Mapping ==

The SE/30 employs 8 × 30-pin SIMM slots organized in a dual-bank architecture that directly affects memory addressing and diagnostic behavior. Bank A consists of the front 4 slots closest to the motherboard edge and must be populated first, while Bank B contains the rear 4 slots behind Bank A and remains optional unless installing more than 4MB RAM. The 32-bit data bus requires 4 SIMMs per bank for full width operation, with memory interleaving supported when using matched SIMMs for improved performance.

Critical configuration rules mandate that all 4 SIMMs within a bank must match capacity and speed (120ns minimum), while banks can have different capacities provided individual bank SIMMs match. A notable exception exists for the 17MB configuration using 256KB SIMMs in Bank A plus 4MB SIMMs in Bank B, which optimizes 1MB video memory allocation. For large capacity installations, the general rule places smaller SIMMs in Bank A and larger SIMMs in Bank B.

=== Address Space Organization ===

The standard SE/30 memory map allocates System RAM from 0x000000-0x3FFFFF (first 4MB base), with 1MB reserved from the system RAM pool for video memory. ROM Space occupies 0x400000-0x4FFFFF, I/O Space spans 0x500000-0xEFFFFF, and Slot Space extends from 0xF900000-0xFEFFFFFF when operating in 32-bit addressing mode. The Glue Logic chip (UI8) controls address decoding through specialized logic working with F258 RAM multiplexers above the ROM slot, with address translation occurring through the 68030's Memory Management Unit.

Address wrapping and mirroring behavior occurs when SIMM slots are partially populated, causing incomplete address decoding where upper address bits become ignored. Address wraparound manifests when accessing beyond physical memory limits, creating specific bit patterns based on which exact address lines are affected. The system wraps to lower addresses when accessing beyond available memory, with the video controller expecting continuous address space that produces visible patterns when address decode fails.