Editing IBM PALM processor (section)

== Memory Map of the Running System ==

The first 128 bytes of RWS are memory-mapped to the four banks of 16 registers (with the active bank window changing with the current interrupt level). The remainder of RWS is general-purpose RAM, with certain addresses reserved for I/O status bytes that the executable ROS keeps up to date.<ref>voidstar.blog, "IBM 5100 / 5110 memory map and acronyms" — cross-verified to SY31-0405 §3.</ref>

{| class="wikitable styled-table" style="width:100%;"
|+'''Selected RWS addresses (5100 / 5110)'''
! Address !! Contents
|-
| $0000–$001F || Register file, interrupt level 0 (R0L0 = IAR; R1L0 = link register)
|-
| $0020–$003F || Register file, interrupt level 1
|-
| $0040–$005F || Register file, interrupt level 2
|-
| $0055 || Printer Status Byte A (low byte of R10L2)
|-
| $0057 || Printer Status Byte B (low byte of R11L2)
|-
| $0060–$007F || Register file, interrupt level 3
|-
| $008F || Tape Status Byte
|-
| $00A8 || Last byte of RWS (5100) — varies; 5110 last byte is $00AA
|-
| $00AC || Address of the RWS / ROS switch routine
|-
| $00AE || Address of the I/O supervisor
|-
| $00E8 / $00E9 || Disk Status Byte A / B (5110 only)
|-
| $0200–$05FF || Display buffer (memory-mapped 64 × 16-character screen)
|}

The I/O supervisor exposes a 14-byte IOCB (I/O Control Block) for each device; the layout is documented at the Stuttgart Computer Museum's IOCB page.<ref>Corti, C., Stuttgart Computer Museum, "IOCB layout".</ref>