Editing Atari Mega ST (section)

=== Memory ===

RAM on the Mega ST is implemented with socketed or soldered DRAM chips, depending on the board revision. The Mega ST2 uses 16 &times; 1 Mbit DRAM chips (organized as 256K &times; 4), while the Mega ST4 uses 32 such chips. The Mega ST1 uses 8 &times; 1 Mbit DRAM chips. Memory access is handled by the MMU (Memory Management Unit, Atari C025913) and the GLUE chip (Atari C025914), which together manage bus arbitration, refresh, and address decoding.

The memory map follows the standard ST layout:

{| class="wikitable"
|-
! Address range !! Function
|-
| $000000–$3FFFFF || ST RAM (up to 4 MB)
|-
| $E00000–$E7FFFF || TOS ROM (192 KB)
|-
| $FA0000–$FBFFFF || Cartridge port ROM space (128 KB)
|-
| $FF8000–$FFFFFF || I/O hardware registers
|}