Editing Apple Desktop Bus (section)

=== Complete Timing Specifications ===
The ADB protocol operates with precise timing requirements for all signal transitions:

{| class="wikitable" style="width:90%; text-align:center;"
|+'''ADB Protocol Timing Parameters'''
! Signal Type !! Duration !! Tolerance !! Description
|-
| Reset pulse || 3000 μs || Minimum || Host pulls bus low for 3 ms or more to reset all devices
|-
| Attention || 800 μs || ±3% || Host pulls bus low to initiate transaction
|-
| Sync || 70 μs || ±10% || Bus high between attention and command
|-
| Bit cell (total) || 100 μs || ±3% || Total time for one bit transmission
|-
| Logic 0 low time || 65 μs || ±3% || Low portion of logic 0 bit cell
|-
| Logic 0 high time || 35 μs || ±3% || High portion of logic 0 bit cell
|-
| Logic 1 low time || 35 μs || ±3% || Low portion of logic 1 bit cell
|-
| Logic 1 high time || 65 μs || ±3% || High portion of logic 1 bit cell
|-
| Stop bit || 0 || Always || Stop bit is always logic 0
|-
| Service Request || 300 μs || Minimum || Device extends stop bit low to assert SRQ
|-
| Tlt (Stop-to-start) || 140-260 μs || Range || Bus high between command and data
|-
| SRQ detection window || 65-300 μs || Range || Period when devices can assert service request
|}