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== Clock & Reset Signal Diagnostics == <templatestyles src="Template:StyledTable/styles.css" /> {| class="wikitable styled-table" style="width:100%; text-align:center;" ! Signal !! Test Point !! Expected Value !! Notes |- | Master oscillator || Crystal Y1 || 14.31818 MHz (NTSC) / 14.18758 MHz (PAL) || Verify with frequency counter or scope |- | ANTIC clock output (ฮฆ0) || ANTIC pin 19 || 1.79 MHz (NTSC) / 1.77 MHz (PAL) || Should be clean square wave |- | CPU clock (ฮฆ2) || 6502C pin 39 || 1.79 MHz (NTSC) / 1.77 MHz (PAL) || Derived from ANTIC; confirms CPU is being clocked |- | RESET || 6502C pin 40 || Pulses LOW at power-on, then HIGH (+5V) || If stuck LOW: check C/R reset network; if stuck HIGH: CPU may not initialise |- | NMI (Non-Maskable Interrupt) || 6502C pin 6 || Normally HIGH; pulses LOW during vertical blank || Stuck LOW prevents boot |- | IRQ || 6502C pin 4 || Normally HIGH; pulses LOW for interrupt service || Stuck LOW prevents boot |- | HALT || 6502C pin 35 || Normally HIGH; goes LOW during DMA || Controlled by ANTIC; if stuck LOW, CPU halted permanently |} '''If no clock signal is present:''' * Check crystal Y1 for correct value and physical damage. * Verify ANTIC has +5V supply and is not in reset. * FREDDIE generates the divided clock โ a dead FREDDIE means no CPU clock.
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