Editing PDP-11/20 Troubleshooting Guide

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[[File:DEC PDP-11-20 at the Computer History Museum.jpg|thumb|right|360px|PDP-11/20 with its KY11-A console (Don DeBold, CC BY 2.0)]]
Faults on a '''[[PDP-11/20]]''' are best worked through from the power supply to the processor, memory and Unibus, with the console lamps as the main instrument. DEC's ''PDP-11/20 System Manual'' describes what each combination of console lamps means, the ''MM11-E Core Memory Manual'' has a troubleshooting chart for the memory, the ''H720 Power Supply and Mounting Box Manual'' explains how the supply protects itself, and the ''KA11 Processor Manual'' gives the clock adjustment and the maintenance tools.<ref name="sm3" /><ref name="mm3" /><ref name="h2" /><ref name="ka5" /> Measure the supply first: most of the processor's symptoms are also what a sick H720 produces.

== Preliminary checks ==
{| class="wikitable styled-table" style="width:70%; text-align:center;"
|+ '''First checks'''
! Symptom !! Probable cause !! Action
|-
| Nothing at all, fans silent || Mains, fuse F1, the key switch, or (H720-E/F) the remote/local power control || Check F1 and the outlet; on E/F models check the circuit breaker and the remote/local setting of the power control
|-
| Fans run, no lamps, no +5 V || Regulator board fuse, crowbar or overcurrent mode, failed switching transistor || See [[PDP-11/20 Power Supply Service]]
|-
| +5 V low (under about 4.5 V), −15 V near −1 to −2 V || The −15 V crowbar has followed the low +5 V || Fix +5 V first
|-
| Lamps on, machine dead, RUN and BUS both steadily lit || Malfunction on the Unibus or in the processor || See "Console lamp combinations"
|}
<ref name="h2" /><ref name="h24" /><ref name="sm3" />

== Power supply faults ==
* +5 V reads zero, or pulses at a low rate. On overload the +5 V regulator switches off until its current falls and then retries; into a short it delivers about 30 A in this mode. If +5 V has risen towards 6 V the crowbar SCR fires and holds the output down until the output capacitors discharge, then the cycle repeats. Either mode looks like a dead supply on a meter. Remove the load (pull the system unit power connectors) and see whether +5 V recovers.<ref name="h22" /><ref name="h24" />
* +5 V crowbar stays fired. If the switching transistor Q1 has failed short, the SCR keeps conducting and fuse F2 on the regulator board eventually opens. Replace Q1 (2N5301) and check the board before fitting a new fuse.<ref name="h24" /><ref name="drw" />
* −15 V missing. The −15 V regulator is turned off and its output crowbarred to about −1 V to −2 V whenever +5 V is below about 4.5 V. DEC did this to protect the core memory. A low or dead +5 V therefore always takes −15 V with it.<ref name="h24" /><ref name="h27" />
* −15 V high. The −15 V regulator has no overvoltage protection; a failed −15 V switch lets the output rise towards the unregulated −22 V to −25 V.<ref name="h24" /><ref name="sm2" />
* Only DC LO asserted. This happens when the +5 V crowbar has fired with the mains present.<ref name="h24" />
Measure the supplies at the backplane against the limits in [[PDP-11/20 General Maintenance]].

== Power-fail and restart ==
The KA11 traps to the power-fail routine when the mains falls below 105 V, and needs 2 ms for power-down; the H720 holds up for 2 ms at full load from the moment AC LO is asserted.<ref name="sm2" /><ref name="h24" /> The supply asserts AC LO when its +25 V raw supply falls to about 18 V or its −25 V raw supply to about 20 V, and its hysteresis means that if AC LO is asserted at 100 V mains it is not released until the mains reaches 103 V.<ref name="h24" />
* Machine halts or restarts at random with no obvious fault. Check the mains voltage under load, then the H720's 22,000 µF reservoir capacitors: a raw supply that sags with load reaches the AC LO threshold early.<ref name="h24" /><ref name="drw" />
* Hangs when an expansion box is switched on or off. The AC LO and DC LO outputs of every H720 are wired together on the Unibus, and DEC requires each extra box's AC LO and DC LO to be connected so that a failure anywhere is seen by the processor. A fault in any box's supply shows up as a system power fail.<ref name="h28" /><ref name="ka57" />

== Console lamp combinations ==
DEC groups the console lamps into display (ADDRESS REGISTER, DATA), control (RUN, BUS) and major states (FETCH, SOURCE, DESTINATION, EXEC). The steady-state combinations tell you who owns the bus:<ref name="sm3" />
{| class="wikitable styled-table" style="width:100%; text-align:center;"
|+ '''RUN and BUS lamps (PDP-11/20 System Manual, section 3.3.1)'''
! RUN !! BUS !! Meaning !! What to check
|-
| Faint glow || Off || Normal running: the processor clock stops and starts with each bus transfer || –
|-
| Fully on || Off || WAIT instruction loop, or the processor in control || Normal in a WAIT; otherwise a program loop
|-
| Off || On || A peripheral holds the bus through an NPR or BR || Normal briefly. DEC notes the BUS lamp is rarely seen except for a bus malfunction or a peripheral holding the bus too long: find the device
|-
| Off || Off || The console has control (HALT, S-INST, S-CYCLE) || Normal when halted
|-
| On || On || Malfunction || Bus fault: remove peripheral controllers one at a time
|}
<ref name="sm3" />
On a HALT instruction the console takes control and the DATA display shows register R0, which identifies which halt a program reached; the ADDRESS REGISTER shows the address of the halt, and the program counter is that address plus 2.<ref name="sm3" />

== Processor and memory ==
* Console EXAM of an address shows zero data and the RUN lamp comes on. The address is odd or does not exist; no trap occurs from the console. Clear it with START in the HALT position. If the address should be real memory, the memory unit is not responding.<ref name="sm3" />
* Memory test failures. Deposit and examine patterns from the console in each 4K unit to find which unit fails. The MM11-E is inhibited by its DC OK signal when the supply voltages are low, so check −15 V and +5 V at the memory before condemning it; then work through the MM11-E section below.<ref name="sm2" /><ref name="mm1" />
* Erratic instruction execution. Check the processor clock: with a WAIT at location 0 running, SCLK L at pin E03F1 on the M728 should have a 280 ns cycle; adjust trimpot R8 on the M728 if not.<ref name="ka59" />
* Fault not obvious from the console. DEC's tools are the MAINDEC diagnostics, with Processor Test 17 as the overall exerciser, and the KM11 maintenance set (W130 and W131 modules), which single-clocks the processor, can disable time-out and supply BUS SSYN, and shows the ISR and BSR time states, MSYN, BSYN, traps and condition codes.<ref name="ka511" /> To watch the processor step through the service states, single-clock it from the KM11 with ENABLE/HALT at ENABLE; at HALT the console always takes control in the service state.<ref name="ka511" />

== MM11-E core memory faults ==
DEC's MM11-E manual says the three memory adjustments rarely need touching unless a module has been replaced, but should be checked before troubleshooting a memory that misbehaves. Before adjusting, check that every module on print MM11-E-06 is in place, look for broken wires and connectors, check that the power buses are not shorted together, and confirm +5 V and −15 V are within 5%. DEC requires the adjustments to be made at 20–30 °C.<ref name="mm1" /> The adjustment values are on [[PDP-11/20 General Maintenance]].
{| class="wikitable styled-table" style="width:100%; text-align:center;"
|+ '''MM11-E troubleshooting chart (DEC-11-HR3A-D, Table 3-2)'''
! Symptom !! Affects !! Possible cause !! Corrective action
|-
| rowspan="8" | Picks up bits || All bits || X-Y current too high || Check V REF and reset per the set-up procedure
|-
| All bits || Strobe too early || Reset STROBE DEL to 210 ns on the M729
|-
| All bits || −15 V input low || Reset or repair the H720 supply
|-
| One bit || Inhibit driver inoperative or inhibit winding open || Repair the G102
|-
| All bits || Threshold too low (less than −5.2 V) || Reset V SLICE to −5.2 V on the G103
|-
| Some bits in one byte || Sense amplifier reset inoperative for that byte || Repair the M729
|-
| 8 or 16 bits || TINH H inoperative || Check the M729 and G225
|-
| All bits at high temperature || Stack thermistor or resistor || Check components and wiring to the G225
|-
| rowspan="8" | Drops bits || All bits || X-Y current too low || Reset V REF or repair the G225
|-
| All bits || Strobe too early or too late || Reset STROBE DEL on the M729
|-
| All bits || Threshold too high || Reset V SLICE on the G103
|-
| All bits, 64 locations || Open line in memory || Ring out the stack (read or write lines)
|-
| All bits, 8 locations || Bad switch or driver || Troubleshoot and repair the G226
|-
| One bit, all words || Bad sense line or sense chain (bus receiver, latch, sense amplifier or bus driver) || Troubleshoot and repair the G102
|-
| Some bits, one byte || STROBE or LOAD inoperative for that byte || Troubleshoot and repair the M729
|-
| All bits at low temperature || Stack thermistor or resistor || Check components and wiring to the G225
|-
| rowspan="4" | No response to MSYN L || – || No device select || Check the M109 jumpers and gates
|-
| – || MSEL not reset on previous cycle || Check the M729 circuits
|-
| – || SSYN not reset on previous cycle || Check the M729 circuits
|-
| – || SSYN not setting || Check the M729 circuits
|-
| Memory always performs a DATIP || All bits || PROTECT L input to the M729 grounded || Check and repair
|}
<ref name="mm3" />
The chart gives V SLICE as −5.2 V, while the adjustment procedure in the same manual specifies −5.3 V ±0.2 V; both figures fall inside the procedure's tolerance.<ref name="mm1" /><ref name="mm3" /> Figures 3-2 and 3-3 of the manual show the normal sense, inhibit and drive waveforms with the failure waveforms dotted in.<ref name="mm3" />

== Loading a program to test the machine ==
The 11/20 starts from paper tape: the bootstrap loader (DEC-11-L1PA-LA) is toggled into core from the console, it loads the absolute loader, and the absolute loader loads binary programs such as the MAINDECs. The bootstrap has two variables that depend on memory size and the reading device, listed in Table 4-2 of the system manual.<ref name="sm4" /> To deposit into consecutive locations, LOAD ADDR the start and press DEP repeatedly; the address increments on each deposit after the first.<ref name="sm3" />

== Related pages ==
* [[PDP-11/20]]
* [[PDP-11/20 General Maintenance]]
* [[PDP-11/20 Power Supply Service]]
* [[PDP-11/20 Documentation]]
* [[PDP-11/34 Troubleshooting Guide]]

== References ==
<references>
<ref name="sm2">Digital Equipment Corporation, ''PDP-11/20 System Manual'', DEC-11-HR1B-D, chapter 2, Tables 2-3, 2-5 and 2-7 ([[:File:PDP-11-20 System Manual (DEC-11-HR1B-D).pdf]]).</ref>
<ref name="sm3">DEC, DEC-11-HR1B-D, chapter 3, Tables 3-1 and 3-2 and section 3.3, console interactions, pp. 3-1 to 3-8.</ref>
<ref name="sm4">DEC, DEC-11-HR1B-D, chapter 4, section 4.2, manual loading, and Table 4-2.</ref>
<ref name="h2">Digital Equipment Corporation, ''H720 Power Supply and Mounting Box Manual'', DEC-11-HR5B-D, chapter 2 ([[:File:H720 Power Supply and Mounting Box Manual (DEC-11-HR5B-D).pdf]]).</ref>
<ref name="h22">DEC, DEC-11-HR5B-D, pp. 2-2 to 2-3, section 2.3.3.1, overcurrent protection.</ref>
<ref name="h24">DEC, DEC-11-HR5B-D, p. 2-4, sections 2.3.3.2 to 2.3.6, crowbar, −15 V regulator, AC LO, DC LO.</ref>
<ref name="h27">DEC, DEC-11-HR5B-D, p. 2-7, section 2.4.2.4, −15 V crowbar circuit.</ref>
<ref name="h28">DEC, DEC-11-HR5B-D, pp. 2-7 to 2-8, sections 2.4.3 and 2.4.4, wired-OR AC LO and DC LO.</ref>
<ref name="drw">Digital Equipment Corporation, ''H720 Power Supply and Mounting Box Engineering Drawings'', 1971, D-CS-H720-0-1 parts list ([[:File:H720 Power Supply and Mounting Box Engineering Drawings (1971).pdf]]).</ref>
<ref name="mm1">Digital Equipment Corporation, ''MM11-E Core Memory Manual'', DEC-11-HR3A-D, first printing August 1970, chapter 3, sections 3.2 to 3.2.5, pp. 3-1 to 3-2 ([[:File:MM11-E Core Memory Manual (DEC-11-HR3A-D).pdf]]).</ref>
<ref name="mm3">DEC, DEC-11-HR3A-D, section 3.3, Figures 3-2 and 3-3 and Table 3-2, pp. 3-2 to 3-3.</ref>
<ref name="ka5">Digital Equipment Corporation, ''KA11 Processor Manual'', DEC-11-HR2B-D, chapter 5 ([[:File:KA11 Processor Manual (DEC-11-HR2B-D).pdf]]).</ref>
<ref name="ka57">DEC, DEC-11-HR2B-D, section 5.7, multiple box systems.</ref>
<ref name="ka59">DEC, DEC-11-HR2B-D, section 5.9, processor clock adjustment.</ref>
<ref name="ka511">DEC, DEC-11-HR2B-D, section 5.11, maintenance tips.</ref>
</references>

[[Category:Digital Equipment Corporation]]
[[Category:Troubleshooting Guides]]