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| release date = June 1987
| release date = June 1987
| discontinued = 1989
| discontinued = 1989
| price        = £875 (1987)
| price        = £999 (excluding VAT, 1987)
| cpu          = ARM2 @ 8 MHz
| cpu          = ARM2 @ 8 MHz
| memory      = 1 MB RAM (expandable to 4 MB)
| memory      = 1 MB RAM (expandable to 4 MB)
| storage      = 3.5" floppy drive (800 KB), optional hard drive
| storage      = 3.5" floppy drive (800 KB)
| display      = 640×512 (16 colours), 640×256 (256 colours), 1152×896 (monochrome)
| sound        = 8-channel stereo, 8-bit
| sound        = 8-channel stereo, 8-bit logarithmic DAC
| os          = Arthur 0.30, later Arthur 1.20 (upgradeable to RISC OS 2)
| dimensions  = 415 mm × 355 mm × 104 mm
| weight      = 8 kg
| os          = Arthur 0.30 (later RISC OS 2.00)
| predecessor  = [[BBC Master]]
| predecessor  = [[BBC Master]]
| successor    = [[Acorn Archimedes A410]], [[Acorn Archimedes A3000]]
| successor    = [[Acorn Archimedes A3000]]
| codename    = Fairway
| model        = A305, A310, A440
}}
}}


The '''Acorn Archimedes A310''' was the first mass-market computer to use a RISC processor, released in June 1987 alongside the A305 and A440 models. Built around Acorn's revolutionary ARM2 processor, the A310 delivered unprecedented performance for its price point, outperforming the Motorola 68000-based competition while maintaining full BBC BASIC compatibility through its advanced operating system.
The '''Acorn Archimedes A310''' was released in June 1987 alongside the A305 and A440 models. The A305 and A310 were launched in June 1987 and were the first RISC CPU-based computers in the world .


== Architecture ==
== Overview ==


The A310's architecture represented a radical departure from conventional microcomputer design. At its core, the ARM2 processor implemented a Reduced Instruction Set Computer philosophy with a streamlined 32-bit architecture. The processor executed most instructions in a single cycle, achieving 4-8 MIPS performance at 8 MHz when contemporary 68000 and 80286 processors struggled to reach 2 MIPS at similar clock speeds.
The Archimedes was described as "the first RISC machine inexpensive enough for home use" and "the first commercially-available RISC-based microcomputer" . Launch prices of the first Archimedes range were A305 at £799, A310 at £999, A410 at £1,399 and A440 at £2,299 (excluding VAT and monitor) .


=== System Components ===
The Archimedes had an ARM processor (originally an abbreviation for 'Acorn RISC Machine'), which would become a vital part of many systems and still is today . The ARM2 32-bit CPU had 26-bit addressing and ran at 8 MHz .


{| class="wikitable styled-table" style="width:70%; text-align:center;"
== Hardware Specifications ==
! Component !! Part Number !! Function !! Key Features
|-
| '''ARM2''' || VL2333-PC10 || 32-bit RISC CPU || 25,000 transistors, 68-pin PLCC, <1W power
|-
| '''MEMC''' || VL7991-PC11 || Memory controller || CAM-based MMU, DMA control, 84-pin PLCC
|-
| '''VIDC''' || VL475-PC12 || Video/sound controller || 4096 colors, 8-channel DMA sound, 88-pin PLCC
|-
| '''IOC''' || VL2966-PC10 || I/O controller || Timers, interrupts, peripherals, 68-pin PLCC
|}


The system employed four custom VLSI chips that Acorn designed specifically for the Archimedes range. These chips communicated via a high-speed local bus operating at 8 MHz, with MEMC coordinating all memory access to prevent conflicts between the processor, video, and sound subsystems.
=== Processor ===
The ARM2 processed about 3x as many instructions per clock cycle as the Intel 80386 and 40% more per clock cycle than the Motorola 68030 . Acorn's publicity claimed a performance rating of 4 MIPS, with Archimedes taking the crown as the fastest microcomputer in the world at the time, able to achieve 4.5 MIPS, although some claimed 18 MIPS .


=== Memory Map ===
=== Memory ===
The A310 had 1 MB memory standard . Despite the A310 being limited to 1 MB of RAM officially, several companies made upgrades to 2 MB and 4 MB, with the smaller upgrades augmenting the built-in RAM and the larger upgrades replacing it entirely .


{| class="wikitable styled-table" style="width:70%; text-align:center;"
=== Architecture ===
|+'''A310 Memory Organization'''
The A310 had an 8MHz ARM2, MEMC1 memory controller, 1MB RAM . The system used custom VLSI chips designed specifically for the Archimedes: ARM2 processor, MEMC memory controller, VIDC video/sound controller, and IOC input/output controller.
! Address Range !! Size !! Function !! Access Speed
|-
| $0000000 – $01FFFFF || 32 MB || Logical RAM space || 2-4 cycles
|-
| $0200000 – $02FFFFF || 1 MB || Physical RAM || Fast page mode
|-
| $1F00000 – $1FFFFFF || 1 MB || I/O space || 8 MHz
|-
| $2000000 – $2FFFFFF || 16 MB || Physical space || DMA/Video
|-
| $3000000 – $33FFFFF || 4 MB || ROM space || 2 cycles
|-
| $3400000 – $3FFFFFF || 12 MB || Expansion ROM || Variable
|}


MEMC implemented an unusual but efficient memory management scheme using a CAM (Content Addressable Memory) array providing hardware page translation without the complexity of a full MMU. This design supported 32 logical pages of 32 KB each, allowing sophisticated memory protection while maintaining single-cycle access for sequential addresses.
=== Display and Sound ===
The 32-bit system was fully capable of displaying 256 colors and 8-bit sounds . Graphical and sound power was a giant step forward over the BBC micro, with 256 colour modes (from a palette of 4096) and 8 channel 8-bit stereo sound .


== Hardware Design ==
== Operating System ==


The A310 motherboard measured 355mm × 245mm and employed a four-layer PCB design to minimize signal interference. The layout positioned the four custom chips in a square formation to minimize trace lengths, with the ARM2 and MEMC chips requiring precise timing relationships.
There were a couple of publicly released versions of Arthur in 1987, 0.30 in June and 1.20 in September . Arthur 1.20 had a desktop written in BASIC which was very limited .


=== ARM2 Processor Details ===
The operating system was in ROM, which meant the computer started very fast, though upgrades could only be carried out when the ROM was changed . For version 2 (October 1988), Arthur was renamed to RISC OS, which featured an updated GUI to enable co-operative multitasking of applications and a much more restrained colour scheme .


The ARM2 processor contained approximately 25,000 transistors fabricated on a 3µm CMOS process. Despite its 32-bit architecture, the chip used only 68 pins and consumed less than 1 watt of power. The processor implemented 27 32-bit registers arranged in multiple banks for rapid context switching during interrupts.
== Expansion ==


{| class="wikitable styled-table" style="width:85%; text-align:center;"
The 300 series required the addition of a backplane to gain expansion slot capabilities. A two slot backplane could be added to the 300 series as an official upgrade, with the possibility of 4-slot backplane being available from third parties . Common expansions included the Acorn AKA01 2 slot backplane, Acorn AKA05 ROM/RAM podule, and Acorn AKA10 I/O podule .
! Feature !! Specification !! Implementation
== Common Issues ==
|-
| '''Pipeline''' || 3-stage || Fetch, decode, execute
|-
| '''Registers''' || 27× 32-bit || 16 visible, banked for modes
|-
| '''Addressing''' || 26-bit || 64 MB address space
|-
| '''Instructions''' || Fixed 32-bit || Conditional execution on all
|-
| '''Barrel shifter''' || 32-bit || Single-cycle shifts/rotates
|-
| '''Multiply''' || 32×32→32 || 2-16 cycles depending on data
|}


The three-stage pipeline allowed the ARM2 to fetch, decode, and execute instructions simultaneously. Conditional execution on all instructions eliminated many branch operations, improving pipeline efficiency. The barrel shifter permitted complex address calculations and bit manipulation in a single cycle, compensating for the limited instruction set.
In the Archimedes A310, Acorn specified three 100uF Tantalum capacitors rated at 16V as decoupling capacitors for the power supply on the motherboard. The voltage rating for these capacitors was under-specified, particularly for C37 which decouples the 12V line . This commonly caused power issues with machines failing to boot correctly.


== Video System ==
The MEMC chip was revised and most Archimedes owners replaced it with the MEMC1a chip which, along with the PAL delivered an approximate 10% performance increase .
 
VIDC provided exceptional graphics capabilities for 1987, supporting multiple resolutions and color depths through programmable video timing. The chip contained sophisticated palette handling and hardware cursor support, with all video data fetched via DMA without processor intervention.
 
=== Display Modes ===
 
{| class="wikitable styled-table" style="width:90%; text-align:center;"
! Mode !! Resolution !! Colors !! Refresh !! Memory !! Bandwidth
|-
| 0 || 640×256 || 2 || 50 Hz || 20 KB || 1 MB/s
|-
| 9 || 640×256 || 16 || 50 Hz || 80 KB || 4 MB/s
|-
| 10 || 640×256 || 256 || 50 Hz || 160 KB || 8 MB/s
|-
| 12 || 640×512 || 16 || 50 Hz || 160 KB || 8 MB/s
|-
| 13 || 640×512 || 256 || 50 Hz || 320 KB || 16 MB/s
|-
| 15 || 640×512 || 16 || 50 Hz || 160 KB || 8 MB/s
|-
| 20 || 640×512 || 16 || 70 Hz || 160 KB || 11.2 MB/s
|-
| 21 || 640×512 || 256 || 70 Hz || 320 KB || 22.4 MB/s
|-
| 23 || 1152×896 || 2 || 75 Hz || 128 KB || 9.6 MB/s
|}
 
Video timing was fully programmable, allowing custom display modes beyond the standard configurations. The chip generated separate horizontal and vertical sync signals compatible with both standard and multisync monitors. Border color and display blanking were software-controlled, enabling overscan effects and smooth mode switching.
 
== Sound System ==
 
The VIDC sound system represented a significant advancement over previous 8-bit computers. Eight independent DMA channels could each play different samples at varying rates and stereo positions.
 
=== Audio Specifications ===
 
{| class="wikitable styled-table" style="width:85%; text-align:center;"
! Parameter !! Specification !! Notes
|-
| '''Channels''' || 8 independent || DMA-driven
|-
| '''Sample format''' || 8-bit µ-law || ~12-bit linear equivalent
|-
| '''Sample rates''' || 3.125 - 48 kHz || Per channel
|-
| '''Stereo positions''' || 7 per channel || Hardware panning
|-
| '''Buffer size''' || 4 words/channel || Interrupt on empty
|-
| '''Output''' || Stereo 3.5mm jack || Line level
|}
 
Each channel supported seven stereo positions (left, center-left, center, center-right, right, and two intermediate positions), enabling sophisticated spatial effects. The logarithmic DAC encoding provided better perceived quality than linear 8-bit systems, approximating 12-bit linear resolution for typical audio material.
 
== Input/Output Systems ==
 
The A310 provided comprehensive I/O capabilities through multiple interfaces. The IOC chip managed most standard peripherals while the motherboard included dedicated controllers for floppy drives and optional hard drives.
 
=== Port Specifications ===
 
{| class="wikitable styled-table" style="width:90%; text-align:center;"
! Interface !! Controller !! Connector !! Speed !! Protocol
|-
| '''Serial''' || 6551 ACIA || 9-pin D-sub || 19200 bps || RS423
|-
| '''Parallel''' || 8-bit latch || 25-pin D-sub || 50 KB/s || Centronics
|-
| '''Floppy''' || WD1772 || 34-pin IDC || 31.25 KB/s || ADFS format
|-
| '''SCSI''' || Optional NCR5380 || 50-pin IDC || 1 MB/s || SCSI-1
|-
| '''Econet''' || 68B54 ADLC || 5-pin DIN || 200 kbps || Network
|-
| '''Mouse''' || Quadrature || 9-pin mini-DIN || 100 Hz || X/Y encoders
|-
| '''Keyboard''' || 8051 MCU || 6-pin mini-DIN || Serial || Custom protocol
|}
 
The WD1772 floppy disk controller operated at 8 MHz, supporting both 250 kbps (double density) and 500 kbps (high density) data rates. The controller interfaced directly with the IOC chip for DMA transfers. The ADFS (Advanced Disc Filing System) implemented a proprietary format storing 800 KB on double-density disks through efficient sector allocation.
 
=== Expansion Bus ===
 
Four 96-pin DIN 41612 expansion slots provided access to the full processor bus. These "podule" slots supported sophisticated expansion capabilities:
 
* '''Bus width:''' 8-bit or 16-bit data transfers
* '''Addressing:''' 24-bit address space per slot
* '''Speed:''' 2 MHz (slow) or 8 MHz (fast) operation
* '''Power:''' +5V @ 200mA, ±12V @ 100mA per slot
* '''Interrupts:''' IRQ and FIQ support
* '''DMA:''' Direct memory access capability
 
Common expansion cards included SCSI interfaces, Ethernet adapters, video digitizers, MIDI interfaces, and ROM/RAM expansion boards. The podule specification allowed automatic configuration, with each card identifying itself to the operating system at startup.
 
== Operating System Evolution ==
 
The A310 initially shipped with Arthur 0.30, a rudimentary operating system providing basic functionality while RISC OS was under development. Arthur included a simple command-line interface, BBC BASIC V interpreter, and essential filing system support.
 
=== Operating System Comparison ===
 
{| class="wikitable styled-table" style="width:90%; text-align:center;"
! Feature !! Arthur 0.30/1.20 !! RISC OS 2.00
|-
| '''Desktop''' || Single-tasking || Cooperative multitasking
|-
| '''Memory management''' || Static allocation || Dynamic areas
|-
| '''Font system''' || Bitmap only || Outline fonts
|-
| '''File systems''' || ADFS, DFS || ADFS, DFS, NetFS, RamFS
|-
| '''Applications''' || Command-line tools || Paint, Draw, Edit included
|-
| '''Window manager''' || Basic windowing || Full WIMP environment
|-
| '''ROM size''' || 512 KB || 2 MB
|}
 
RISC OS 2.00, released in April 1989, transformed the A310 into a sophisticated GUI-based system. The operating system resided in ROM, providing instant startup and immunity from disk corruption. The modular architecture allowed individual components to be updated or replaced without affecting system stability.
 
== Memory and Performance ==
 
The A310 shipped with 1 MB of RAM as standard, organized as four 256K×9-bit SIMMs providing byte-wide error detection. Memory bandwidth limitations significantly affected system performance in high-resolution modes.
 
=== Performance Impact by Display Mode ===
 
{| class="wikitable styled-table" style="width:85%; text-align:center;"
! Mode !! Resolution !! DMA Overhead !! CPU Performance
|-
| 0 || 640×256×2 || 6% || 94% of maximum
|-
| 12 || 640×512×16 || 25% || 75% of maximum
|-
| 13 || 640×512×256 || 50% || 50% of maximum
|-
| 21 || 640×512×256 @ 70Hz || 70% || 30% of maximum
|}
 
Memory expansion to 4 MB required replacing the standard modules with 1M×9-bit SIMMs. The system reserved the top 32 KB of physical memory for screen display, with additional allocations for sound buffers and system workspace. Contemporary benchmarks demonstrated the A310's superiority, with Dhrystone yields of 4100 iterations per second compared to 1800 for a 16 MHz 80286.
 
== Power Supply ==
 
The A310 employed a linear power supply rated at 45 watts continuous output. The transformer-based design provided excellent regulation but generated substantial heat.
 
=== Power Specifications ===
 
{| class="wikitable styled-table" style="width:70%; text-align:center;"
! Rail !! Voltage !! Current !! Usage
|-
| Primary || +5V || 6A || Logic circuits
|-
| Drive || +12V || 1.5A || Floppy/hard drives
|-
| Serial || -5V || 100mA || RS423 levels
|-
| Auxiliary || -12V || 50mA || Optional peripherals
|}
 
The conservative design contributed to long-term reliability, though electrolytic capacitors eventually degrade, causing ripple and regulation problems that manifest as system instability or startup failures.
 
== Manufacturing Variants ==
 
Acorn produced several PCB revisions addressing design issues and reducing costs:
 
{| class="wikitable styled-table" style="width:85%; text-align:center;"
! Issue !! Production Period !! Changes !! Known Problems
|-
| 1 || Jun-Dec 1987 || Original design || Timing marginal, Arthur bugs
|-
| 2 || Jan-Sep 1988 || PAL integration || Podule compatibility
|-
| 3 || Oct 1988-1989 || RISC OS ready || Battery placement
|-
| 4 || 1989 || Cost reduced || Some incompatibilities
|}
 
Component substitutions occurred throughout production. Early machines used Motorola 68B51 serial chips, later replaced with Rockwell 65C51 variants. RAM manufacturers varied between Samsung, NEC, and Hitachi, with minor timing differences affecting marginal systems.
 
== Known Issues ==
 
Several design decisions affected long-term reliability:
 
* '''Battery leakage:''' 3.6V NiCd CMOS battery corrodes PCB traces after 10-15 years
* '''Thermal stress:''' Linear PSU operates near limits, stressing capacitors
* '''Keyboard controller:''' 8051 firmware corruption requires chip replacement
* '''ROM bugs:''' Arthur versions exhibit memory corruption and crashes
* '''Podule timing:''' Some expansion cards require Issue 2+ motherboards
 
Early ROM versions contained numerous bugs. Arthur 0.30 and 1.20 exhibited memory corruption under specific circumstances, random crashes during disk access, and compatibility problems with certain podule cards. RISC OS 2.00 resolved most issues but introduced new problems with some existing software.
 
== General Maintenance ==
{{Main|Acorn Archimedes A310 General Maintenance}}
 
Regular maintenance extends operational lifetime significantly. Critical tasks include CMOS battery replacement before leakage occurs, power supply capacitor inspection for bulging or leakage, and ventilation path cleaning to prevent thermal stress. The keyboard requires periodic cleaning to maintain reliable operation, while the floppy drive needs lubrication and alignment checks every 2-3 years.
 
== Troubleshooting ==
{{Main|Acorn Archimedes A310 Troubleshooting}}
 
Common failures follow predictable patterns. Power supply problems manifest as startup failures or random resets, usually traced to degraded capacitors in the main filter section. Video corruption indicates VIDC timing issues or RAM failures, diagnosed through systematic memory testing. Floppy drive errors result from alignment drift or WD1772 controller chip failure, requiring careful adjustment or component replacement.
 
== Capacitor Replacement Guide ==
{{Main|Acorn Archimedes A310 Capacitor Replacement Guide}}
 
After 35+ years, electrolytic capacitors require replacement. Critical components include:
* '''PSU main filter:''' 4700µF 25V
* '''PSU auxiliary:''' 1000µF 16V (×3), 470µF 25V (×2)
* '''Motherboard:''' 100µF 16V (×6), 47µF 16V (×8), 10µF 25V (×4)
* '''High-voltage:''' 100µF 200V (×2) in PSU primary
 
== Technical Legacy ==
 
The A310 established ARM processors in the personal computer market, demonstrating RISC architecture advantages over complex instruction set competitors. While commercial success remained limited outside education markets, the technical innovations influenced subsequent computer designs. ARM processors, refined through successive generations, now dominate mobile computing, validating Acorn's architectural decisions from 1987.


== See Also ==
== See Also ==
* [[Acorn Archimedes A305]]
* [[Acorn Archimedes A305]]
* [[Acorn Archimedes A410]]
* [[Acorn Archimedes A440]]
* [[Acorn Archimedes A440]]
* [[Acorn Archimedes A3000]]
* [[Acorn Archimedes A3000]]
* [[BBC Master]]
* [[BBC Master]]
== External Links ==
* [https://chrisacorns.computinghistory.org.uk/Computers/A300.html Chris's Acorns: Acorn Archimedes A300 series]
* [https://www.computinghistory.org.uk/ Centre for Computing History]


[[Category:Acorn Computers]]
[[Category:Acorn Computers]]

Latest revision as of 17:35, 29 September 2025


Acorn Archimedes A310
Acorn Archimedes A310
Specifications
ManufacturerAcorn Computers Ltd
TypePersonal Computer
ReleasedJune 1987
Discontinued1989
Intro price£999 (excluding VAT, 1987)
CPUARM2 @ 8 MHz
Memory1 MB RAM (expandable to 4 MB)
Storage3.5" floppy drive (800 KB)
Display—
Sound8-channel stereo, 8-bit
OS / FirmwareArthur 0.30, later Arthur 1.20 (upgradeable to RISC OS 2)
PredecessorBBC Master
SuccessorAcorn Archimedes A3000

The Acorn Archimedes A310 was released in June 1987 alongside the A305 and A440 models. The A305 and A310 were launched in June 1987 and were the first RISC CPU-based computers in the world .

Overview

[edit | edit source]

The Archimedes was described as "the first RISC machine inexpensive enough for home use" and "the first commercially-available RISC-based microcomputer" . Launch prices of the first Archimedes range were A305 at £799, A310 at £999, A410 at £1,399 and A440 at £2,299 (excluding VAT and monitor) .

The Archimedes had an ARM processor (originally an abbreviation for 'Acorn RISC Machine'), which would become a vital part of many systems and still is today . The ARM2 32-bit CPU had 26-bit addressing and ran at 8 MHz .

Hardware Specifications

[edit | edit source]

Processor

[edit | edit source]

The ARM2 processed about 3x as many instructions per clock cycle as the Intel 80386 and 40% more per clock cycle than the Motorola 68030 . Acorn's publicity claimed a performance rating of 4 MIPS, with Archimedes taking the crown as the fastest microcomputer in the world at the time, able to achieve 4.5 MIPS, although some claimed 18 MIPS .

Memory

[edit | edit source]

The A310 had 1 MB memory standard . Despite the A310 being limited to 1 MB of RAM officially, several companies made upgrades to 2 MB and 4 MB, with the smaller upgrades augmenting the built-in RAM and the larger upgrades replacing it entirely .

Architecture

[edit | edit source]

The A310 had an 8MHz ARM2, MEMC1 memory controller, 1MB RAM . The system used custom VLSI chips designed specifically for the Archimedes: ARM2 processor, MEMC memory controller, VIDC video/sound controller, and IOC input/output controller.

Display and Sound

[edit | edit source]

The 32-bit system was fully capable of displaying 256 colors and 8-bit sounds . Graphical and sound power was a giant step forward over the BBC micro, with 256 colour modes (from a palette of 4096) and 8 channel 8-bit stereo sound .

Operating System

[edit | edit source]

There were a couple of publicly released versions of Arthur in 1987, 0.30 in June and 1.20 in September . Arthur 1.20 had a desktop written in BASIC which was very limited .

The operating system was in ROM, which meant the computer started very fast, though upgrades could only be carried out when the ROM was changed . For version 2 (October 1988), Arthur was renamed to RISC OS, which featured an updated GUI to enable co-operative multitasking of applications and a much more restrained colour scheme .

Expansion

[edit | edit source]

The 300 series required the addition of a backplane to gain expansion slot capabilities. A two slot backplane could be added to the 300 series as an official upgrade, with the possibility of 4-slot backplane being available from third parties . Common expansions included the Acorn AKA01 2 slot backplane, Acorn AKA05 ROM/RAM podule, and Acorn AKA10 I/O podule .

Common Issues

[edit | edit source]

In the Archimedes A310, Acorn specified three 100uF Tantalum capacitors rated at 16V as decoupling capacitors for the power supply on the motherboard. The voltage rating for these capacitors was under-specified, particularly for C37 which decouples the 12V line . This commonly caused power issues with machines failing to boot correctly.

The MEMC chip was revised and most Archimedes owners replaced it with the MEMC1a chip which, along with the PAL delivered an approximate 10% performance increase .

See Also

[edit | edit source]
[edit | edit source]
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