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DECsystem-10

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DECsystem-10
A DECsystem-10 with the KI10 processor console and DECtape drives (Gah4, CC BY-SA 4.0)
Specifications
ManufacturerDigital Equipment Corporation
Type36-bit time-sharing mainframe
Discontinued1983 (cancellation announced)[1]
CPUKA10 (1040, 1050, 1055); KI10 (1070, 1077); KL10 (1080 to 1099)[2][3]
MemoryCore memory cabinets on the memory bus: KA10 systems to 256K words, KI10 systems to 4096K words[2]
Storage—
Display—
Sound—
PowerThree-phase mains; a KL10-C processor alone takes about 21.6 kVA[4]
OS / FirmwareTOPS-10[1]
PredecessorPDP-10

The DECsystem-10 is Digital Equipment Corporation's name for complete 36-bit time-sharing systems built on the PDP-10 architecture. DEC's 1971 technical summary sells five configurations under the name: the DECsystem-1040, 1050 and 1055 with the KA10 processor and the 1070 and 1077 with the newer KI10.[2] The ECL KL10 processor followed in the 1080 and 1090 and their variants; DEC's 1080/1090 system description dates from June 1975.[5][3] DEC announced the cancellation of the PDP-10 line in 1983, and reports put sales at about 1500 DECsystem-10s by the end of 1980.[1]

A DECsystem-10 is several cabinets of processor, memory and peripherals tied together by the memory bus, the I/O bus and a power control bus. Restoring one means dealing with three-phase power distribution, regulated supplies in every cabinet, core memory with its own margins and adjustments, and air-flow and door interlocks that shut the system down. Those are covered in DECsystem-10 Power Supply Guide, DECsystem-10 General Maintenance and DECsystem-10 Troubleshooting Guide.

Models

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DECsystem-10 configurations in 1971 (DEC technical summary, p. 16)
1040 1050 1055 1070 1077
Processors 1 KA10 1 KA10 2 KA10 1 KI10 2 KI10
Core memory (K words) 32–256 64–256 80–256 96–4096 128–4096
Hardware instructions 366 366 366 377 377
Paging and virtual memory No No No Yes Yes
Interrupt service time 6 µs 6 µs 6 µs 3 µs 3 µs

[2]

KL10-based DECsystem-10 designations (KL10 Maintenance Guide)
System Processor
1080 KL10-A (model A) running TOPS-10
1088 Dual-processor 1080
1090 KL10-B (model A) or KL10-D (model B) running TOPS-10
1090T KL10-BC running TOPS-20 (ARPANET systems only)
1091 KL10-E or KL10-R (model B) with cache, running TOPS-10
1095 KL10-E/R (PW) with the MCA25 cache and pager and MG20 memory
1099 SMP multiprocessor (1090) system

[3] DEC's KL10 notes: the KL10-PA ("model A") is the basic ECL processor; the KL10-PV ("model B") adds extended addressing, more microcode and a faster clock; the KL10-PW is a model B modified for the MCA25.[3]

Hardware

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Processors

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The KA10 and KI10 share the DECsystem-10 monitor, software and most peripherals, so a KA10 system can be upgraded to a KI10 without changing user programs.[6] The KI10 adds paging, a 4096K-word physical address space, four register blocks and programmable logic voltage margins: its DC logic supply can be set under program control to any of 64 levels, so diagnostics can run across a range of voltages without manual adjustment.[2][7]

The KL10 is an ECL processor. On the 1080 and 1090 a PDP-11/40 console front end (KD11-A processor) talks to it through a DTE20 interface, loads its microcode and boots it.[5] The DECsystem-10 KL10 machines use external memory cabinets on the original PDP-10 memory bus and the tall PDP-10 cabinets, where the DECSYSTEM-20 versions use internal memory in shorter cabinets.[1]

Memory

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DECsystem-10 main memory is magnetic core in separate cabinets, each with several ports to processors and data channels (up to eight on the MH10).[8] The 1971 range used the ME10 (16K words per bank, 1 µs cycle) and the MD10 mass core (64K words per cabinet, expandable to 128K).[2] Later cabinets include the MF10 and the MH10.[9] DEC's MH10 is a coincident-current 3-wire core memory of 64K to 256K 37-bit words (36 data bits and parity), cycle time 1.2 µs, compatible with every DECsystem-10 processor and memory. A single MH10 cabinet weighs 409 kg and dissipates 2400 W.[8]

Safety and power features

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The KA10 and KI10 detect a power failure and interrupt the processor so that the monitor can save its state. The KI10 monitors all three phases and can restart automatically when power returns. Temperature sensors in the equipment cause a power shutdown on overheating.[7] On the KL10-C the power control shuts the system down for insufficient air flow at any of four sensors, a tripped CPU power breaker or an open cooling-assembly door, and holds it off for at least 13 seconds.[10]

Surviving systems

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A working KI10 system was formerly at Living Computers: Museum + Labs in Seattle.[1] Some of that museum's systems later went to the SDF Interim Computer Museum, which offers online access to PDP-10-family machines.[1] The PiDP-10 is a front-panel replica that runs PDP-10 simulators on a Raspberry Pi, with ITS and TOPS-10 software.[11]

Documentation

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Bitsavers holds the KA10, KI10 and KL10 maintenance manuals, print sets and memory manuals; see DECsystem-10 Documentation.[9]

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  • DECsystem-1090: KL10 processor and MH10 memory cabinets (Retro-Computing Society of Rhode Island, CC BY-SA 3.0)
    DECsystem-1090: KL10 processor and MH10 memory cabinets (Retro-Computing Society of Rhode Island, CC BY-SA 3.0)
  • MF10 core memory indicator panel (Jkbw, public domain)
    MF10 core memory indicator panel (Jkbw, public domain)
  • H866 memory bus terminator (Jkbw, CC BY-SA 3.0)
    H866 memory bus terminator (Jkbw, CC BY-SA 3.0)
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References

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  1. ↑ 1.0 1.1 1.2 1.3 1.4 1.5 "PDP-10", Wikipedia, en.wikipedia.org/wiki/PDP-10. Cancellation in 1983, sales by 1980, TOPS-10, 10xx packaging and memory, Living Computers KI10, SDF Interim Computer Museum.
  2. ↑ 2.0 2.1 2.2 2.3 2.4 2.5 Digital Equipment Corporation, DECsystem-10 Technical Summary, 1971, pp. 9–16 and 51–53 (File:DECsystem-10 Technical Summary (1971).pdf). Configurations, comparison table "DECsystem-10 at a glance", ME10 and MD10 memories.
  3. ↑ 3.0 3.1 3.2 3.3 Digital Equipment Corporation, KL10 Maintenance Guide, Volume I, EK-OKL10-MG-003, April 1985, general information p. 11, "KL10-Based System and Processor Designations" (File:KL10 Maintenance Guide Volume 1 (EK-OKL10-MG-003).pdf).
  4. ↑ Digital Equipment Corporation, DECSYSTEM-20 Power System Description, EK-PWR20-SD-001, April 1976, pp. PWR20/1-4 and 1-9 (File:KL10-C Power System Description (EK-PWR20-SD-001).pdf). KL10-C electrical requirements.
  5. ↑ 5.0 5.1 Digital Equipment Corporation, DECsystem-1080/1090 System Description, EK-1080U-SD-003, first edition June 1975, third edition January 1977, contents and section 4.3, bitsavers.org. Console processor subsystem and DTE20.
  6. ↑ DEC, DECsystem-10 Technical Summary, 1971, p. 37. KA10 and KI10 central processors.
  7. ↑ 7.0 7.1 DEC, DECsystem-10 Technical Summary, 1971, p. 49. Safety features and programmable voltage margins.
  8. ↑ 8.0 8.1 Digital Equipment Corporation, MH10 Maintenance Manual, EK-MH10-MM-003, August 1977, pp. 1-1 to 1-8 (File:MH10 Core Memory Maintenance Manual (EK-MH10-MM-003).pdf). Description and Table 1-1 specifications.
  9. ↑ 9.0 9.1 Directory listings, bitsavers.org/pdf/dec/pdp10/, retrieved 2 October 2026.
  10. ↑ DEC, EK-PWR20-SD-001, pp. PWR20/2-5 to 2-6. Fault conditions and shutdown.
  11. ↑ "PiDP-10" repository README, github.com/obsolescence/pidp10.
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