MC68030 Enhanced 32-Bit Microprocessor User's Manual Third Edition 1990
The MC68030 Enhanced 32-Bit Microprocessor User's Manual is Motorola's reference manual for the MC68030 processor, published for Motorola by Prentice Hall, Englewood Cliffs, New Jersey. The hosted copy is the Third Edition, © 1990 Motorola, Inc., ISBN 0-13-566423-3; it has 608 PDF pages and is paginated by section.[1]
The MC68030 is the processor in several Macintosh models, among them the Macintosh SE/30, Macintosh IIci and Macintosh Classic II. The manual is the manufacturer's source for the chip's pinout, supply pins and maximum ratings.
Contents
editSixteen sections: 1 Introduction; 2 Data Organization and Addressing Capabilities; 3 Instruction Set Summary; 4 Processing States; 5 Signal Description; 6 On-Chip Cache Memories; 7 Bus Operation; 8 Exception Processing; 9 Memory Management Unit; 10 Coprocessor Interface Description; 11 Instruction Execution Timing; 12 Applications Information; 13 Electrical Characteristics; 14 Ordering Information and Mechanical Data; M68000 Family Summary; Index.[1]
Maximum ratings and thermal data
edit| Rating | Symbol | Value |
|---|---|---|
| Supply voltage | VCC | −0.3 to +7.0 V |
| Input voltage | Vin | −0.5 to +7.0 V |
| Operating temperature | TA | 0 to 70 °C |
| Storage temperature | Tstg | −55 to 150 °C |
A footnote to the supply-voltage rating reads: "A continuous clock must be supplied to the MC68030 when it is powered up." The thermal resistance of the ceramic PGA package is given as 30 °C/W junction to ambient and 15 °C/W junction to case, both marked as estimates.[1]
Supply pins and decoupling
editTable 12-7 groups the VCC and GND pins by the circuits they feed:[1]
| Pin group | VCC | GND |
|---|---|---|
| Address bus | C6, D10 | C5, C7, C9, E11 |
| Data bus | L6, K10 | J11, L9, L7, L5 |
| ECS, SIZx, DS, AS, DBEN, CBREQ, R/W | K4 | J3 |
| FC0-FC2, RMC, OCS, CIOUT, BG | D4 | E3 |
| Internal logic, RESET, STATUS, REFILL, misc. | H3, F2, F11, H11 | L8, G3, F3, G11 |
Motorola suggests a combination of low-, middle- and high-frequency capacitors placed as close to the MC68030 as possible, for example 10 µF, 0.1 µF and 330 pF in parallel, and the same treatment for the other VLSI devices in the system. It warns that a poor connection between the processor's supply pins and the board's power planes results in increased assertion delays on external signals, reduced noise margins and potential errors in internal logic.[1]
Ordering information
edit| Package | Frequency (MHz) | Temperature | Order number |
|---|---|---|---|
| Pin grid array (RC suffix) | 20.0 | 0-70 °C | MC68030RC20 |
| Pin grid array (RC suffix) | 25.0 | 0-70 °C | MC68030RC25 |
| Pin grid array (RC suffix) | 33.33 | 0-70 °C | MC68030RC33 |
| Ceramic surface mount (FE suffix) | 20.0 | 0-70 °C | MC68030FE20 |
| Ceramic surface mount (FE suffix) | 25.0 | 0-70 °C | MC68030FE25 |
| Ceramic surface mount (FE suffix) | 33.33 | 0-70 °C | MC68030FE33 |
What this manual does not contain
editSection 13 states that the DC electrical characteristics, power figures and AC timing specifications are in a separate Motorola document, MC68030EC/D, MC68030 Electrical Specifications, which the wiki does not hold. So this manual has no supply current, logic levels or setup and hold times.[1] It also has nothing specific to any computer.
Related pages
edit- High Level Programmers Guide to the 68000 1992
- Programming the 68000 1986
- SAMS 68000 68010 68020 Primer 1987
- Category:Apple Programming Documentation
Download: MC68030 Users Manual 3rd Edition 1990.pdf (20 MB)
References
edit- ↑ 1.0 1.1 1.2 1.3 1.4 1.5 1.6 1.7 Motorola, MC68030 Enhanced 32-Bit Microprocessor User's Manual, Third Edition, Prentice Hall, 1990, ISBN 0-13-566423-3, MC68030 Users Manual 3rd Edition 1990.pdf. Title and copyright pages (PDF pp. 3-4); Table 12-7 and decoupling, p. 12-46; Section 13, p. 13-1; Section 14.1, p. 14-1.