Editing Sega Master System (Model 1) (section)

== System Architecture ==
{| class="wikitable styled-table" style="width:70%; text-align:center;"
! Sub-system !! Specification (Master System Model 1)
|-
| '''CPU''' || Z80A 8-bit @ 3.58 MHz (NTSC) / 3.55 MHz (PAL) • 16-bit address – 64 KB space
|-
| '''VDP''' || Sega 315-5124 (NTSC) / 315-5246 (PAL)  
TMS9918-derived: 2× pattern tables, 32 sprites (8 per scan-line)  
VRAM 16 KB (dual 8 KB SRAM, 5 ns page registers)
|-
| '''Palette''' || 64 colours (6-bit RGB) – 32 on-screen (background & sprite)
|-
| '''Audio''' || TI SN76489 PSG (integrated into VDP) – 3 square + 1 noise  
Expansion pin-out for YM2413 FM (used in JP “FM Unit” & Mark III)
|-
| '''Main RAM''' || 2 × 8 KB HM6264 (work-RAM) @ ~150 ns
|-
| '''Cartridge ROM''' || Up to 4 Mbit/512 KB (LoROM/HiROM mapper chips: Sega 315-5235, 315-5208, etc.)
|-
| '''BIOS''' || 8 KB mask ROM ver 1.3 (NA/EU) — intro menu + hidden Snail Maze (hold ↑+1+2)
|-
| '''I/O''' || 2× DE-9 game-pad, RF-UHF & 8-pin AV, Card slot (36-pin), 50-pin cart, 35-pin EXT
|}

=== Exact 64 KB CPU Memory-Map (Model 1) ===
{| class="wikitable styled-table" style="width:70%; text-align:center;"
|+''Z80 Address Space''
! Range !! Size !! Purpose / Notes
|-
| $0000 – $3FFF || 16 KB || '''ROM–0''' (Cartridge / Card / BIOS)
|-
| $4000 – $7FFF || 16 KB || '''ROM–1''' (bank-selectable via mapper)
|-
| $8000 – $BFFF || 16 KB || '''ROM–2''' (bank-selectable)
|-
| $C000 – $DFFF || 8 KB || '''Work-RAM''' (on-board)
|-
| $E000 – $FFFF || 8 KB || Mirror of $C000 – $DFFF
|}

''Mapper registers'' are written through bogus addresses $FFFC–$FFFF (upper bits decoded by on-cart ASICs such as 315-5196).

=== BIOS Entry Points (v1.3) ===
{| class="wikitable styled-table" style="width:70%; text-align:center;"
! Address !! Routine
|-
| $0000 || Soft reset  →  Sega splash &amp; checksum
|-
| $00A8 || PSG mute / init
|-
| $0150 || Card detect loop
|-
| $0200 || Hidden game “Snail Maze” (activate ↑+1+2 at logo)
|}