Editing SuperCPU and Turbo Accelerators (section)

== Historical overview ==
{| class="wikitable sortable" style="font-size:90%; text-align:center; margin:0 auto;"
! Accelerator !! CPU / Core<br />(clock) !! RAM on card !! First retail !! Bus interface !! Notes
|-
| '''Turbo Master CPU''' || NMOS 6502 @ ≈4 MHz || none || 1990 || Edge connector || “Bank-stealing” waits during VIC DMA; requires stub ROM for KERNAL patching.
|-
| '''Flash 8''' || WDC 65C816 @ 8 MHz || none || 1993 || Edge connector || German kit; hardware wait-state generator for VIC access.
|-
| '''SuperCPU v1 / v2''' || WDC 65C816 @ 20 MHz (switch-able 1×/5×/20×) || up to 16 MB (SuperRAMCard) || 1996 / 1997 || Edge connector pass-through || Hitachi HD6120 glue logic (v1) → CMD FPGA (v2); fully transparent timing compensation.
|-
| '''Turbo Process''' || WDC 65C02 @ ≈3.5 MHz || none || 1996 || Internal daughter-board || Installation required desoldering the 6510; limited commercial run.
|-
| '''Chameleon 64 (FPGA)''' || 65816-compatible soft-core @ ~48 MHz* || 16 MB SDRAM || 2011 || Docking-station / cartridge || Also functions as stand-alone FPGA C-64. *Effective “Turbo” factors ×1…×11 selectable.
|-
| '''Ultimate 64 / U64 Elite''' || FPGA SoC (65816-like) @ 48 MHz || 16 MB SDRAM || 2018 || Replacement main-board || Whole-system re-implementation; per-cycle compatible “soft-6510” plus Turbo. 
|}

*Clock figures are the raw CPU frequency; '''effective speed-up''' depends on VIC-II DMA stealing and memory-wait strategies.*