SuperCPU and Turbo Accelerators
| |
| Caption | The Creative Micro Designs SuperCPU v2 with optional 16 MB SuperRAMCard |
|---|---|
| Type | External plug-in accelerators (cartridge port) |
| Designer | See individual entries (CMD, Schnedler Systems, Eberhard Poensgen, Individual Computers…) |
| Manufacturer | Multiple (1990-present) |
| First released | 1990 (Turbo Master CPU) – 2010 s (FPGA-based solutions) |
| Latest revision | — |
| Operating voltage | 5 V DC from C-64 expansion port |
| Layers / PCB | — |
| Compatibility | Commodore 64, 64C, SX-64 and (in most cases) Commodore 128 (in C-64 mode) |
| Features | — |
| Model No. | — |
The SuperCPU and other “turbo” accelerators replace, augment or bypass the original 1 MHz 6510 of the Commodore 64/128, giving the 8-bit computer a dramatic speed-up while preserving almost full software compatibility. Approaches range from simple 4 MHz 6502 cards of the early 1990 s to modern FPGA-based cartridges with 48 MHz 65816 cores and cycle-perfect VIC-II synchronisation.
Historical overview
[edit | edit source]| Accelerator | CPU / Core (clock) |
RAM on card | First retail | Bus interface | Notes |
|---|---|---|---|---|---|
| Turbo Master CPU | NMOS 6502 @ ≈4 MHz | none | 1990 | Edge connector | “Bank-stealing” waits during VIC DMA; requires stub ROM for KERNAL patching. |
| Flash 8 | WDC 65C816 @ 8 MHz | none | 1993 | Edge connector | German kit; hardware wait-state generator for VIC access. |
| SuperCPU v1 / v2 | WDC 65C816 @ 20 MHz (switch-able 1×/5×/20×) | up to 16 MB (SuperRAMCard) | 1996 / 1997 | Edge connector pass-through | Hitachi HD6120 glue logic (v1) → CMD FPGA (v2); fully transparent timing compensation. |
| Turbo Process | WDC 65C02 @ ≈3.5 MHz | none | 1996 | Internal daughter-board | Installation required desoldering the 6510; limited commercial run. |
| Chameleon 64 (FPGA) | 65816-compatible soft-core @ ~48 MHz* | 16 MB SDRAM | 2011 | Docking-station / cartridge | Also functions as stand-alone FPGA C-64. *Effective “Turbo” factors ×1…×11 selectable. |
| Ultimate 64 / U64 Elite | FPGA SoC (65816-like) @ 48 MHz | 16 MB SDRAM | 2018 | Replacement main-board | Whole-system re-implementation; per-cycle compatible “soft-6510” plus Turbo. |
- Clock figures are the raw CPU frequency; effective speed-up depends on VIC-II DMA stealing and memory-wait strategies.*
Technical principles
[edit | edit source]- Bus arbitration
The VIC-II still needs 40 CPU cycles per raster line for video-DMA. Turbo accelerators therefore:
- Stretch φ2 low-time (Turbo Master/Flash 8) so that fast code runs only when the VIC is idle.
- Shadow RAM on-board and replay writes to the real C-64 DRAM during idle slots (SuperCPU).
A fast 16-bit 65816 runs from zero-wait SRAM while the VIC keeps reading the slow motherboard RAM.
- Memory mapping
Most units expose extra RAM through the standard \$FFxx banking lines (EXROM/GAME or REU registers). The SuperCPU’s *SuperRAMCard* appears at \$DF00 and can be logically mapped in 64 KB pages, giving GEOS 2.0 a full 4–16 MB workspace.
- Compatibility layers
- IO shadowing – writes to \$D000–\$DFFF are mirrored so that timers/sprites still update at 1 MHz cadence.
- KERNAL patch – accelerators supply a tiny ROM that intercepts IRQ entry/exit to resynchronise with VIC safe-lines (Turbo Master).
- Turbo OFF switch – most devices fall back to 1 MHz for cycle-exact demos or $DD00 colour‐cycle loading schemes.
Benchmarks
[edit | edit source]| Accelerator | BASIC “PI Test” (User port loop-back) |
Assembly Dhrystone (32-bit) |
Notes | ||
|---|---|---|---|---|---|
| Seconds (1×) | Speed-up | DMIPS (1×) | Speed-up | ||
| Un-accelerated | 68 s | 1.0× | 0.18 | 1.0× | Reference C-64 (1982) |
| Turbo Master CPU | 19 s | 3.5× | 0.55 | 3.0× | Wait-state hit at badlines |
| Flash 8 | 11 s | 6.2× | 0.95 | 5.3× | Full 8 MHz except colour fetch |
| SuperCPU @20 MHz | 3.4 s | 20× | 2.9 | 16× | GEOS boots in ≈4 s! |
| Chameleon ×11 | 2.9 s | 23× | 3.2 | 18× | “Cycle exact” turbo |
| U64 Turbo ×48 | 1.5 s | 45× | 5.8 | 32× | RAM in SDRAM, VIC DMA virtualised |
(Data averaged from user reports and SysInfo v4.4 runs.) Exact numbers vary with cache settings, memory contention and whether *bad-line* throttling is enabled.
Software support
[edit | edit source]- GEOS 2.0–2.1 detects the SuperCPU and patches its VBL handler for 20 MHz operation, giving near-instant screen redraw.
- Turbo Macro Pro and 64tass include “SPDXL” assemblers that emit 65816 op-codes to exploit the 24-bit address space.
- Games/Demos – few require the accelerator, but *Metal Dust* (2005) famously needs the SuperCPU’s 65816 and 4 MB RAM.
- CP/M cartridge clones *cannot* coexist with turbo cards – both expect exclusive use of the expansion bus.
Power & heat considerations
[edit | edit source]High-speed 65xx CPUs and external SRAM draw up to 800 mA at 5 V. Original Commodore “brick” PSUs are marginal; modern switch-mode supplies or a C64 Saver are strongly recommended. The SuperCPU v1’s CPLD runs hot (≈70 °C) – later v2 fixed this with a cooler FPGA and heat-spreaders.
Availability in 2025
[edit | edit source]- Original CMD SuperCPUs are scarce (≈ €800 used).
- Flash 8 occasionally appears as unpopulated PCBs on German forums.
- Chameleon 64 V2 is still manufactured by Individual Computers (~€250).
- Ultimate 64 Elite (replacement main-board with Turbo) ships in small batches several times a year.
- Commodore 64 Ultimate (FPGA-based re-creation full system with turbo up to 64MHz) started shipping in November 2025 and is still available (~€298).
DIY and open-source projects
[edit | edit source]- SaRuMan 65816 core – open VHDL clone of the SuperCPU memory controller.
- Pi1541-Turbo – over-clocks the 6510 only during disk-I/O by injecting a 2 MHz clock on φ2.
- Kola-Max – bread-board prototype using a W65C816 @ 14 MHz plus dual-port SRAM (proof-of-concept, 2023 GitHub release).