Editing IBM PALM processor (section)

== Bus and Memory Map ==

[[File:PALM RWS memory map.gif|right|thumb|320px|RWS (Read-Write Storage) memory map of the IBM 5110 as seen by PALM. The first 128 bytes are the memory-mapped register-bank window; the remaining RWS is general-purpose RAM. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]

[[File:PALM SAR bits.gif|right|thumb|320px|Storage Address Register (SAR) bit-field layout. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]

PALM uses '''three physically separate buses''' on the A1 backplane:

* '''Storage Address Bus''' — 16 bits, output from PALM, reaches RWS and Executable ROS.
* '''Storage R/W Bus''' — 18 bits (16 data + 2 parity), bidirectional between PALM and storage.
* '''I/O Bus''' — 8 bits + parity, plus control strobes (Put Strobe, Get Strobe, Control Strobe, Op Code E); bidirectional between PALM and Base I/O / peripheral cards.

The memory map is unusual in that '''ROS is accessed as both memory and I/O''':

* '''RWS (RAM)''' — accessed only through the Storage Address Bus / Storage R/W Bus.
* '''Executable ROS''' — accessed through the Storage Address Bus for instruction fetch '''and''' as an I/O device (address 2) for the bank-switching scheme.
* '''Common / Language ROS''' (APL and BASIC interpreters) — accessed '''only''' as an I/O device (address 1), '''never''' as memory. PALM treats the language ROS as a peripheral and fetches interpreter code through the I/O bus, byte-by-byte.

This is an architecturally distinctive design: it means the language interpreters cannot be jumped into directly — they must be invoked through the I/O subsystem.