IBM PALM processor

IBM PALM

PALM processor card from an IBM 5110 (slot J2), with 13 metal-can gate arrays. Photograph: Christian Corti, Stuttgart Computer Museum
Specifications
Developer	IBM, Boca Raton, Florida
Manufacturer	IBM
Type	Microprogrammed processor on one circuit card
Introduced	1973 (SCAMP prototype); 1975 (IBM 5100)
Architecture	16-bit instructions; 8-bit ALU; four interrupt levels, each with sixteen 16-bit registers
Data width	16-bit storage data path plus 2 parity bits; 8-bit I/O bus plus parity
Address width	16 bits
Clock rate	15.1 MHz oscillator; 66.2 ns clock pulses
Package	Circuit card with 13 metal-can gate arrays
Used in	IBM 5100, IBM 5110, IBM 5120

The IBM PALM is the processor of the IBM 5100, IBM 5110 and IBM 5120. It is not a single chip but a circuit card carrying 13 metal-can gate arrays and a few other parts, which runs a 16-bit microinstruction set from read/write storage or read-only storage (ROS). IBM's maintenance manuals never use the name PALM: the 5100 manual calls the card in slot G2 the controller and defines it as "the microinstruction processor within the 5100 Portable Computer", and the 5110 manual calls the card in slot J2 the processor card. The name appears in IBM's internal documents, such as H. J. Myers' 1977 Instructions for the Use of Assembler Generator, General Assembler, General Loader, which uses "the PALM computer" as its example target machine, and IBM's description of the microinstruction set ("The micro-instructions selected for PALM are composed of sixteen bit control words").

Origin

The PALM board first appeared in SCAMP, a portable APL prototype built in 1973. According to the Smithsonian, which holds the prototype, IBM's General Systems Division asked the IBM Scientific Center in Palo Alto in late 1972 to build a machine that would raise the profile of APL. Paul Friedl and his colleagues spent six months on it, using existing parts, including "a PALM microprocessor board from IBM in Boca Raton, Florida"; its APL emulated the IBM 1130 version. SCAMP was the prototype for the IBM 5100, announced in 1975.

The SCAMP prototype at the Smithsonian National Museum of American History.

IBM's 1977 design paper on the 5100 says the prototype's APL ran on an 1130 emulator, and that the team later chose the System/370 APL, APLSV, and in late June 1974 began writing an emulator for it, which occupied less than 10K of executable ROM.

How IBM describes the processor

The design paper describes the processor as "a fast two-chip 8-bit processor" with "49 16-bit microinstructions" and four interrupt levels. The instruction count matches the maintenance manual, whose alphabetical list in Appendix C has 49 mnemonics. The card itself carries 13 gate arrays, so "two-chip" does not describe the card as built.

The ALU is 8 bits wide and the arithmetic and logical instructions work on the low-order byte of a register; registers, instructions and the storage data path are 16 bits.

Clock and cycle timing

Clock-cycle diagram. (Diagram: Christian Corti, Stuttgart Computer Museum)

The 5100 maintenance manual gives the timing:

• A 15.1 MHz oscillator produces 66.2 ns multiclock cycle (MCC) pulses. On the card photographed above, the oscillator is a CTS Knights can marked 15.0912 MHz.
• Each machine cycle is an I (instruction) phase followed by an E (execute) phase.
• The I phase is three I cycles of 3, 8 and 3 MCC. In I cycle 1, register 0 of the current program level is loaded into the storage address register (SAR); in I cycle 2 the microinstruction is read from read/write storage or executable ROS into the operation register; in I cycle 3 the address is incremented by two and written back to register 0.
• The E phase is one to five E cycles of 3 or 8 MCC each, 3 to 40 MCC in total, depending on the op code. Only read/write storage can be addressed during E cycles.

IBM's microinstruction description says its execution-time table (Figure 11) assumes a storage cycle of 529.6 ns, which is eight MCC pulses, and that "execution times will be slightly larger when micro-instructions are executed out of FSU ROS". Corti has a hand-copied table he believes is Figure 11; it gives times such as 2.65 µs for CTL and EMIT, 3.97 µs for MOVE, LDHD, STHD, CLRI, ADDI, SUBI and SETI, 4.63 µs for the register ALU instructions, GETB and the indirect loads and stores, and 5.30 µs for the jumps, each with a second, smaller figure in brackets that the copy does not explain.

Registers and interrupt levels

IBM calls the interrupt levels program levels. Each has sixteen 2-byte registers, which are on the processor card but are addressed as the lowest 128 bytes of read/write storage. Register 0 of each level is the instruction address register; the other fifteen are general purpose. IBM's microinstruction description reserves register 1 as the link register by convention.

Program levels (5100 maintenance manual p. 4-17)

Level	Devices on the 5100
0	Normal operation
1	Serial I/O adapter and asynchronous communications adapter
2	Tape and printer
3	Keyboard

The design paper lists the same levels from highest priority down: keyboard; tape and printer; communications and serial I/O; normal operation. The processor checks the interrupt request lines after each microinstruction and takes the highest-numbered request; the system allows only one active request per level. On the 5110, level 2 also serves the diskette. Because each level has its own registers, switching level saves no state.

Instruction set

Every instruction is one 16-bit halfword. The top four bits give the op code; the rest hold register numbers, a device address, an immediate byte or a modifier.

PALM op codes (IBM mnemonics)

Op code	Fields	Instructions
0	Rx, Ry, ALU modifier	MVM2, MVM1, MVP1, MVP2, MOVE, AND, ORB, XOR, ADD, SUB, ADDS1, ADDS2, HTL, LTH, GETR, GETA
1	Device address, command	CTL
2, 3	Rx, address	LDHD, STHD (direct, first 256 halfwords)
4	Device address, Ry, modifier	PUTB
5, 6, 7	Rx, Ry, modifier	STHI, LDBI, STBI (indirect)
8	Rx, byte	EMIT
9	Rx, mask	CLRI
A	Rx, byte	ADDI
B	Rx, mask	SETI
C	Rx, Ry, jump modifier	The 16 jumps: JLE, JLO, JEQ, JNO, JALL, JALLM, JNOM, JHAM, JHI, JHE, JHL, JSB, JSN, JSNM, JSM, JHSNM
D	Rx, Ry, modifier	LDHI
E	Device address, Ry, modifier	GETB, GETRB; with device address 0, SHFTR and ROTR
F	Rx, byte	SUBI

The indirect instructions can add 1 to 4 to the address register or subtract 1 to 4 from it (modifier 0 to 7), or leave it unchanged (8 and above). ADDI adds the immediate byte plus one, so a data byte of 00 adds 1; SUBI likewise subtracts the byte plus one. GETA adds an even value from 0 to E, derived from the input byte, to a register.

Jumps are skips

The 5100 manual defines the jump instructions this way: "A jump microinstruction tests for a condition and jumps over (skips) the next sequential microinstruction if that condition is met. If the jump condition is not met, the microinstruction following the jump microinstruction is executed and the address of the jump microinstruction plus 4 is stored in register 1 for use as a return address in case the next sequential microinstruction (after the jump microinstruction) branches to a subroutine." The tests look at the low-order byte of the registers; modifiers 8 to F give the same tests with the jump on a false condition.

There is no call, return or unconditional jump instruction and no hardware stack. A branch is a load into register 0, and IBM's description gives MOVE R0,R1 as the return from a subroutine. A subroutine that itself uses a conditional jump must save register 1 first, because every jump that is not taken overwrites it.

Assemblers

The Myers document of 1977 describes IBM's assembler generator, general assembler and loader, with PALM as the worked example. Alfred Arnold's Macro Assembler AS added an IBM PALM target in version 1.42 build 231 (October 2022).

Buses and storage

PALM data flow: read data register, storage address register, operation register, storage data register, ALU register, 8-bit ALU, control ROS and the register file. (Diagram: Christian Corti, Stuttgart Computer Museum)

The processor connects to the rest of the machine through three buses: a 16-bit storage address bus to read/write storage and executable ROS, an 18-bit storage read/write bus (two bytes, each with a parity bit), and a 9-bit data bus in and 9-bit data bus out (one byte plus parity) to the base I/O card. The display adapter reads storage by cycle steal.

IBM's 5100 had two kinds of ROS. Executable ROS holds the microprograms the processor runs directly: the bring-up diagnostic, the tape and printer I/O microprograms and the language emulators. The denser non-executable (language) ROS holds the APL and BASIC interpreters and is read through the I/O bus as a device, with GET microinstructions. On the 5100 the BASIC ROS is on card C4, the common ROS on E2 and the APL ROS on C2, D2 and D4.

Reading the language ROS on the 5100 works like this:

1. A control instruction to device address 1 selects the ROS space.
2. Two put instructions load the 16-bit ROS address, high byte first, into the address register on the E2 card. The top six bits decode an address range of 30K bytes.
3. Two get instructions return the 16 bits, high byte first.
4. The second get also increments the address register, so sequential reads need no new address.

The 5100 manual is not consistent about which bit selects which ROS. Its theory section (p. 4-19) says bus-out bit 4 selects BASIC and common ROS and bit 5 selects APL; its Control Command Data Table (p. C-4) gives command bit 12, which becomes bus-out bit 4, for APL and bit 13 for BASIC and common. On the 5110, bits 4, 5 and 6 select BASIC, APL and common ROS respectively.

On the 5110, read/write storage is laid out as registers (0000-007F), common language control area, display buffer (0200-05FF), system control area (0600-07FF) and user area. Corti's list of fixed locations includes the printer status bytes at 0055 and 0057, the tape status byte at 008F, the highest available storage address at 00A8, the last storage address at 00AA, the address of the routine that enters executable ROS at 00AC and the I/O supervisor at 00AE.

I/O addressing

A device address is one of four X lines and one of four Y lines, giving 16 addresses. Some addresses (1, B, C, D and E on the 5100) also take a subdevice address, so that one address can serve up to eight devices. The 5100 and 5110 use different address maps.

IBM 5100 device addresses (5100 manual p. 3-81 and Appendix C)

Address	Lines	Device
0	X0Y0	Controller (G2)
1	X0Y1	Non-executable ROS (BASIC C4, APL C2, D2, D4)
4	X1Y0	Keyboard and the APL/BASIC switch
5	X1Y1	Printer
8	X2Y0	Expansion feature (communications adapter or serial I/O adapter)
E	X3Y2	Tape units
F	X3Y3	All I/O (resets individual devices)
2, 3, 6, 7, 9, A, B, C, D		Not assigned

IBM 5110 device addresses (IOCB byte 0, 5110 manual p. 3-11)

Address	Device
00	Video display and processor
01	Common and language ROS
03	Diskette sort
04	Keyboard
05	Printer
06	BSCA
07	Parallel I/O
0A	Serial I/O
0C	Print plot
0D	Diskette drive
0E	Tape drive
02, 08, 09, 0B, 0F	Not used

IOCB byte 1 selects the subdevice: for the diskette, hex 80, 40, 20 and 10 are drives 1 to 4; for tape, 80 is the internal drive and 40 the external one. The 5110's error code summary lists async communications and BSC under device address 8, although the IOCB table gives BSCA as 06, and under APL it reports the tape, serial I/O and diskette as device address 0 with a subdevice code, where BASIC reports their own addresses (E, A and D).

I/O transfers are signalled by strobes: a control strobe marks a command byte on bus out, a put strobe marks a data byte, the device answers with a get strobe, and the op code E line flags non-data transfers such as status.

Physical implementation

The card in the photograph, from a 5110, carries 13 square metal-can gate arrays, each marked with a seven-digit IBM part number and "IBM 22", arranged in five rows. Besides these there are two larger white ceramic packages marked 2410086-C (date codes 7825 and 7828), four smaller black DIPs, the CTS Knights 15.0912 MHz oscillator, and resistor packs. The edge of the card is marked 1607136A9458YG41.

Gate arrays on the photographed card (read from the photograph)

Row	Left	Centre	Right
1	2706507	(oscillator)	1554466
2	5564251	(two 2410086-C packages)	2706506
3	5564251	1554469	5564255
4	2706504	2706503	1554468
5	1554470	2706505	1554467

Part 5564251 appears twice, so the 13 arrays are 12 different parts. IBM's manuals do not say which array does what.

The controller card has jumper positions for use in a 5100 or a 5110. It sits in slot G2 on the 5100's A1 board and in slot J2 on the 5110, where J2 on the 5100 is the display card, so take slot numbers from the right machine's manual. The 5120's logic manual, which calls the machine the 5110 Model 3, also shows the processor card at A1J2 with a 15.1 MHz oscillator.

Main A1 board cards

Function	5100 slot	5110 slot
Processor (controller)	G2	J2
Display	J2	G2
Base I/O	F2	H2
Executable ROS	H2 (BASIC, I/O and diagnostics), H4 (APL)	L2, feature ROS K4
Language ROS	C4 (BASIC), C2, D2, D4 (APL), E2 (ROS adapter and common ROS)	F2 (common and language), E4 (APL)
Read/write storage	K2, K4, L2, L4, M2, M4, N2, N4	M2, M4, N2, N4
I/O cable driver	A2	A2

Sources for the table: 5100 manual pp. 3-81 and 4-19; 5110 manual pp. 3-5 and 3-18.

The 5110 power supply provides +5 V, −5 V, +8.5 V, +12 V and −12 V.

Emulated instruction sets

The APL and BASIC interpreters are not written in PALM code. Executable ROS holds emulators that run the interpreters from the language ROS.

For APL, IBM's design paper describes adopting the System/370 APLSV interpreter and writing an emulator for it. Corti, who disassembled the 5110's APL executable ROS, describes it as "mainly a System/360 emulator that executes the APL interpreter in 360 code from the non-executable ROS", and notes that it can also run code from read/write storage. For BASIC, Tom Stepleton, who recovered the 5100's executable ROS, describes the interpreter as a modified version of IBM's System/3 BASIC running on an emulated System/3.

Diagnostic features

A storage parity error, a bus parity error or an invalid device address raises a machine check, which stops the processor and lights PROCESS CHECK. On the 5110 a machine check jumper from J2-S07 to J2-S09 on the A1 board can be removed so that the processor carries on after such errors; IBM warns that results can then be misleading.

The 5100's DISPLAY REGISTERS switch shows the processor register area in hexadecimal on the screen. On the 5110, the Diagnostic Control Program is loaded by holding CMD, pressing HOLD and then the minus key on the numeric pad; it can display (D) and alter (A) any location in read/write storage, and so the registers. From there, ATTN followed by CMD and × enters DCP diagnostic mode. Two CE switches inside the 5110, run and step, reached by removing the top cover, let a service engineer stop and step the processor.

Reading the ROS

The processor cannot read executable ROS as data. Stepleton recovered a 5100's executable ROS by starting the machine with the CE run switch set to single-step and DISPLAY REGISTERS on, which leaves the first 512 bytes of executable ROS on the screen, then pulling the seven highest-order address lines to ground through 100 Ω resistors to show each other 512-byte block, and photographing each screen. The resulting images of the 5100's executable and non-executable ROS are on the Internet Archive.

The language ROS can be read by software, because it is an I/O device. Corti publishes a short PALM program, entered through the DCP, that copies the APL ROS into read/write storage (control byte hex 04 selects APL ROS, 08 BASIC and 02 common on the 5110), from where the DCP can write it to diskette.

Related pages

• IBM 5100, IBM 5110, IBM 5120
• IBM 5100 Maintenance Guide, IBM 5110 Maintenance Guide, IBM 5120 Maintenance Guide
• IBM 5100 Maintenance Information Manual, IBM 5110 Maintenance Information Manual, IBM 5120 Computing System Logic Manual, IBM 5100 Portable Computer Design (1977)