File:IBM 5100 Portable Computer Design (1977).pdf

The IBM 5100 Portable Computer Design — A. J. Cubbon, IBM General Systems Division, Rochester. Paper presented at the APL ITL Symposium, Endicott, New York, 11–13 January 1977, Volume 2, marked IBM Internal Use Only, pages 52–56 (IBM document reference 77A000835).

This is IBM's own contemporaneous engineering account of the IBM 5100, written eighteen months after the machine shipped, and it is the earliest public description of the 5100's processor and storage architecture by the people who built it. It is the primary source for several figures that appear nowhere in the customer-facing or CE documentation:

• The processor is described by IBM as "a fast two-chip 8-bit processor" with 49 16-bit microinstructions operating on four interrupt levels — a description that sits awkwardly beside the thirteen bipolar gate arrays visible on the physical controller card, and which is discussed on the IBM PALM processor page.
• Interrupt priority order: 1) Keyboard; 2) Tape and Printer; 3) Communications and Serial I/O; 4) Normal Operations.
• "The only hardware specially designed for the 5100 is the power supply and the covers." The keyboard is the standard IBM solid-state keyboard from the System/32 and 3740; the read/write storage is the same part used in System/32 and some System/370 models; the ROM is the same technology as the 3740's.
• The 48K-bit-per-chip FET ROM that made the machine possible, and a maximum capacity of 248K bytes of storage in the desktop unit.
• The three-level language architecture, and the decision history behind APL on the 5100 — two IBM 1130 APL implementations were evaluated and rejected before the team settled on APLSV from System/370 in late June 1974, writing the emulator and interface code in under six months and in less than 10K of ROM.
• The 5100 was announced in September 1975 and made available worldwide in April 1976.
• The nonexecutable ROS is reached through the I/O adapter, using a GET microinstruction rather than a storage address register — the architectural quirk that makes the language interpreters unreachable by a direct jump.

The paper's own reference is to IBM 5100 Maintenance Information Manual SY31-0405-2 (1976), an earlier edition of the manual also hosted here.

Scanned by bitsavers.org and mirrored at the Internet Archive as item bitsavers_ibmapl5100ignJan77_468072. Hosted here so that the IBM 5100, IBM 5110, IBM 5120 and IBM PALM processor pages can cite a copy that will not move.

Copyright International Business Machines Corporation, 1977. IBM has never released this material under a free licence and has not, as far as is known, formally abandoned copyright in it. It is hosted here on the same basis as the rest of this wiki's manual archive: an out-of-print internal technical paper for a product withdrawn in 1982, reproduced for the non-commercial repair and preservation of machines IBM no longer supports. If you are the rights holder and want this taken down, please say so and it will be removed.