Editing IBM PALM processor (section)

== Physical Implementation ==

The PALM module is a single '''multi-layer printed circuit board''' with a gold-plated edge connector that mates with the A1 system backplane (in the 5110 documentation, it is identified as '''Card J2 — Controller'''). The board carries:

* '''13 × bipolar masterslice gate arrays''' in square metal-can packages.
* '''3 × conventional TTL DIPs'''.
* '''1 × round metal-can device''' (most plausibly the 15.1 MHz oscillator can — likely but not explicitly confirmed in published sources).

The gate arrays are the heart of the implementation.

=== Dutchess Masterslice Gate Arrays ===

The 13 gate arrays on the PALM board are IBM's '''"Dutchess"''' masterslice — an uncommitted-logic-array (ULA) family fabricated by IBM at its bipolar facility (most likely IBM East Fishkill, New York, though this is not explicitly stated in published sources for PALM specifically).

Dutchess specifications:

{| class="wikitable styled-table" style="width:100%;"
|+'''IBM Dutchess masterslice gate array'''
! Parameter !! Value
|-
| Logic family || Bipolar, Schottky-TTL-compatible
|-
| Supply voltage || +5 V
|-
| Gate count per array || ~134 logic gates
|-
| Internal logic mix || 60 × three-input NAND + 40 × four-input NAND + 34 × two-input NOR off-chip drivers
|-
| Propagation delay || ≈ 10 ns per gate
|-
| Package || Square metal can with leadframe
|-
| Personalisation || Metal mask (final aluminum interconnect layer) — the same wafer can be cut into different logic functions by changing only the metal layers
|}

A '''masterslice''' (also known as a sea-of-gates ULA in later terminology) is a wafer pre-fabricated with a fixed array of unconnected transistors. The specific logic function of each chip is set by the metal interconnect layers added at the end of fabrication — this lets IBM build 13 different gate-array functions on the PALM board from the same underlying silicon.

Dutchess was IBM's bipolar workhorse masterslice family for small-system controllers in the early 1970s and predates the larger IBM ECL families used in System/370 mainframes.

[[File:IBM 5100 overhead view.jpg|right|thumb|320px|IBM 5100 chassis interior — the PALM card mounts on the A1 backplane alongside ROS, RWS and I/O cards. The PALM card carries 13 bipolar gate arrays in metal cans on a single multi-layer PCB. Image: Wikimedia Commons, public domain.]]

=== Identified ICs on the PALM Board ===

The 13 Dutchess gate arrays are visible and labelled with IBM part numbers in Christian Corti's high-resolution photograph of the J2 controller card. The IBM part-number format on this generation of Dutchess parts is '''aaaaaa IBM ''nn''''' where '''aaaaaa''' is a 7-digit IBM part number identifying the specific personalisation of the masterslice, and '''nn''' is the IBM family designator (here, '''22''' — denoting the Dutchess family in this configuration). A second line gives a date / lot code in the form '''1-yyy nnnn''' where '''yyy''' appears to be a 3-digit week-of-fab code and '''nnnn''' a serial sequence.

The following IC identifications are transcribed directly from the J2 card photograph. Identification of '''which logical function''' each part performs (ALU, register file, microcode sequencer, etc.) is documented in IBM's SY31-0405 (5100 MIM) and SY34-0193 (5120 CSLM) — but cannot be derived from the photograph alone, and is listed below as '''not yet mapped'''.

{| class="wikitable styled-table" style="width:100%;"
|+'''Identified ICs on the PALM (Card J2) controller card'''
! Position (row, col) !! IBM part number !! Family !! Date / lot code !! Logical function (from CSLM) !! Notes
|-
| 1, 1 (top-left) || '''2706597''' || IBM 22 || 1-841 1062 || Not yet mapped || Same part also at position 4, 1
|-
| 1, 3 (top-right) || '''1554466''' || IBM 22 || 1-849 2247 || Not yet mapped ||
|-
| 2, 1 || '''5564251''' || IBM 22 || 1-849 2865 || Not yet mapped || Same part also at position 3, 1
|-
| 2, 3 || '''2706506''' || IBM 22 || 1-842 1304 || Not yet mapped ||
|-
| 3, 1 || '''5564251''' || IBM 22 || 1-849 2865 || Not yet mapped ||
|-
| 3, 2 (centre) || '''1554469''' || IBM 22 || 1-849 2746 || Not yet mapped ||
|-
| 3, 3 || '''5564255''' || IBM 22 || 1-839 0937 || Not yet mapped ||
|-
| 4, 1 || '''2706597''' || IBM 22 || 1-847 2327 || Not yet mapped ||
|-
| 4, 2 || '''2706503''' || IBM 22 || 1-839 0923 || Not yet mapped ||
|-
| 4, 3 || '''1554468''' || IBM 22 || 1-849 2631 || Not yet mapped ||
|-
| 5, 1 (bottom-left) || '''1554470''' || IBM 22 || 1-844 6469 || Not yet mapped ||
|-
| 5, 2 || '''2706505''' || IBM 22 || 1-842 1516 || Not yet mapped ||
|-
| 5, 3 (bottom-right) || '''1554467''' || IBM 22 || 1-843 1454 || Not yet mapped ||
|}

That gives '''13 Dutchess gate arrays''' (with two repeats — '''2706597''' appears twice and '''5564251''' appears twice — leaving '''11 unique masterslice personalisations''' across the 13 sockets). The repeats are consistent with multiple functions implemented from the same masterslice metal-mask design (the same gate array used twice for byte-paired data paths, for example).

==== Other identified board devices ====

Three smaller devices are visible in the upper-middle region of the J2 card, between the row-1 and row-2 Dutchess arrays. These are the '''3 conventional TTL DIPs''' referenced by Wikipedia and PC Magazine.

{| class="wikitable styled-table" style="width:100%;"
|+'''Smaller ICs on the PALM board (transcribed from the J2 card photograph)'''
! Position !! Marking !! Device type !! Notes
|-
| Upper-middle, left || '''210086-C''', LC 7676.20, 7828 CT || Small DIP || Function not identified from photograph alone
|-
| Upper-middle, right || '''M-210086-C''', LC 7676/20, 7825 2 CT || Small DIP || Same base part number as above; "M-" prefix variant
|-
| Top-centre (green-marked) || Round metal-can with green dot indicator || Crystal oscillator can || Most plausibly the '''15.1 MHz master oscillator''' that produces the 66.2 ns clock pulse. The green dot is consistent with an IBM marking convention for tuned / specified crystals
|}

The "210086-C" and "M-210086-C" markings appear on small DIPs with date codes 7825 / 7828 (the 25th and 28th week of 1978), which is consistent with this specific J2 card being from a 1978 5110 — the date codes are slightly later than the row-1 gate array codes (which include weeks 841, 842, 843, 844, 847, 849 of 1978 by the "1-yyy" convention).

The Stuttgart photograph also shows a board edge marking '''16078496458VG41''' (probably an IBM card serial / FRU number) and additional small surface-mount components and decoupling capacitors near the right edge of the board.

==== Reading the IBM 22 family designator ====

The '''IBM 22''' family designator on every Dutchess part on this card is consistent across the entire 13-IC complement, confirming they are all the same masterslice variant. Different metal-mask personalisations produce the different 7-digit base part numbers (2706597, 1554466, 5564251, 2706506, 1554469, 5564255, 2706503, 1554468, 1554470, 2706505, 1554467) but the underlying silicon is the same Dutchess wafer.

The Dutchess gate count (~134 logic gates per chip) and the 13-chip board complement therefore give the PALM processor an effective gate count of approximately '''13 × 134 ≈ 1,740 logic gates of bipolar Schottky-TTL logic''' — comparable in raw gate count to the early-generation single-chip CPUs of the same era (Intel 8080 ≈ 4,500 transistors / equivalent to a few hundred gates; PALM has more gates but spread across 13 packages).

=== Function Blocks of PALM ===

[[File:PALM dataflow.gif|center|thumb|640px|Data-flow diagram of the IBM PALM processor reverse-engineered by Christian Corti from an actual 5110 controller card. Shows the Read Data Register (RDR), Storage Address Register (SAR), Operation Register, Storage Data Register (SDR), the 8-bit-wide Arithmetic Logic Unit, the Control ROS Unit, the four-banked register file, and the connections to the three external buses (Storage Address Bus, Storage R/W Bus, and I/O Data Bus). (Diagram: Christian Corti, Stuttgart Computer Museum, ©1999–2017, used with attribution.)]]

The Stuttgart Computer Museum's reverse-engineered data-flow diagram of the PALM module identifies the following logical function blocks. The exact one-to-one mapping of these blocks onto the 13 Dutchess gate arrays is documented in IBM's '''SY31-0405 Maintenance Information Manual''' (5100) and '''SY34-0193 Computing System Logic Manual''' (5120) — but is not extracted in any widely-mirrored secondary source. Restorers needing this mapping must consult those PDFs directly.

{| class="wikitable styled-table" style="width:100%;"
|+'''PALM internal function blocks'''
! Block !! Width !! Function
|-
| '''Read Data Register (RDR)''' || 18 bits || Latch for data read from RWS or ROS (16 + 2 parity)
|-
| '''Storage Address Register (SAR)''' || 16 bits || Holds the address of the current storage access
|-
| '''Operation Register (Op Reg)''' || 16 bits || Holds the current instruction (fed to the control ROS for microcode lookup)
|-
| '''Storage Data Register (SDR)''' || 8 bits || Latch for the byte to be written to RWS (write side of the R/W bus)
|-
| '''ALU Register (A)''' || 16 bits || First operand to the ALU; also the ALU output destination
|-
| '''Arithmetic Logic Unit (ALU)''' || 8 bits || Performs ADD, SUB, AND, OR, XOR, NOT — the ALU is 8 bits wide; 16-bit operations are done in two passes
|-
| '''Control ROS''' || Width unverified || The microcode store on the controller card; the Op Reg indexes into this ROS to produce the control word that drives the rest of the cycle. The 256 × 32-bit figure that previously appeared on this page is a Wikipedia talk-page rumour not confirmed by SY31-0405-3
|-
| '''Register File''' || 16 × 16 × 4 = 64 × 16 bits || General-purpose registers — 16 per interrupt level × 4 levels
|-
| '''Oscillator / Clock generator''' || — || 15.1 MHz crystal-controlled oscillator producing the 66.2 ns clock pulse
|-
| '''Interrupt Level Logic''' || — || Detects pending interrupts on levels 1, 2, 3 and arbitrates which bank is currently active
|}

The 8-bit-wide ALU is one of PALM's most distinctive features — a 16-bit machine with an 8-bit-wide arithmetic data path. Sixteen-bit ADD or SUB therefore takes two ALU passes (one per byte), with carry propagation between passes managed by the control ROS sequencer.