Editing IBM PALM processor (section)

== Microcode and Emulated Instruction Sets ==

PALM is best described as a '''microprogrammed processor''' that runs three layered instruction sets at different times:

# '''Native PALM ISA''' (16-bit halfword instructions, decoded by the control ROS on the controller card) — used by IBM's own diagnostics, the GENASM-assembled microcode, and the executive ROS itself.
# '''IBM System/360 subset''' — implemented by an emulator written in native PALM microcode, sitting in the executable ROS. Used only by the APL environment.
# '''IBM System/3 Model 6 subset''' — implemented by a separate emulator in PALM microcode. Used only by the BASIC environment.

=== The System/360 Emulator (APL only) ===

The APL executable ROS contains an IBM System/360 emulator written in PALM microcode. The non-executable APL ROS (cards C2 / D2 / D4 on the 5100) contains the APL interpreter '''as System/360 object code''', which the executive ROS interprets opcode-by-opcode.

This is confirmed by two independent reverse-engineering efforts:

* '''Christian Corti''' (Stuttgart Computer Museum) disassembled the executive ROS in his `aplros.asm` file: "The APL executable ROS is mainly a System/360 emulator that executes the APL interpreter in 360 code from the non-executable ROS."
* '''Brett W. Hill''' (voidstar.blog) reviewed the same disassembly and found '''only System/360 opcodes''' in the dispatch handlers — no System/370-specific instructions.

The earlier widely-circulated claim that PALM contained an "IBM System/370 emulator" is '''not borne out by direct examination of the executive ROS'''. The confusion arises because IBM's APL implementation on mainframes (APLSV) ran on System/370 — but the 5100's port of APLSV was compiled / re-targeted to System/360 object code for execution on PALM, not S/370 code.

The full System/360 opcode subset implemented by the emulator is not published; the canonical source for the actual subset is Corti's `aplros.asm` file at `ftp://ftp.informatik.uni-stuttgart.de/pub/cm/ibm/ibm5110/`. Inference from public material:

* '''Out of scope''': floating-point hardware (APL uses software FP routines), decimal arithmetic, privileged S/360 instructions (SVC, LPSW, storage protection).
* '''In scope''': integer and logical instructions, the addressing modes APL needs, character / packed-data operations the interpreter exercises.

=== The System/3 Emulator (BASIC only) ===

The BASIC environment is built on a separate System/3 Model 6 emulator. The BASIC interpreter is itself System/3 object code, and the executable BASIC ROS interprets that code via the System/3 emulator.

=== Native PALM ISA Word Size ===

Native PALM instructions are '''16-bit halfwords'''. An older internet rumour (preserved in the Wikipedia talk page) claims that the control ROS on the PALM card itself is "32 bits wide" internally — but this claim cannot be confirmed in any primary source the wiki has access to. The SY31-0405-3 MIM describes the control ROS unit functionally but does not state its width. '''Treat the "32-bit internal microcode" figure as unverified.''' What is verified is that the ISA exposed to the executable ROS and to GENASM-generated PALM programs is the 16-bit halfword instruction set documented in IBM "Chapter 2" and in SY31-0405-3 Appendix C.