Editing Acorn Z80 Second Processor (section)

=== Test points ===

{| class="wikitable styled-table" style="width:100%; text-align:left;"
|+'''Test points on the Z80 board (service manual section 6.1)'''
! TP !! Signal !! What it shows
|-
| TP1 || CLOCK || 6 MHz clock to Z80 pin 6
|-
| TP2 || ROM || ROM select; low for about 0.25 s after BREAK
|-
| TP3 || M1 || Instruction fetch cycles, also used in interrupt handling
|-
| TP4 || MREQ || Memory access
|-
| TP5 || PCS || Parasite chip select to the Tube, through the desynchronising logic
|-
| TP6 || HCS || Host chip select to the Tube
|-
| TP7 || WAIT || ROM reads and simultaneous HCS/PCS events
|-
| TP8 || RAS || Row address strobe, present on every memory and refresh cycle
|-
| TP9 || CAS || Column address strobe, absent during refresh
|}