Editing IBM 5100 (section)

=== The Processor ===

'''IBM does not use the name "PALM" anywhere in the 5100 service documentation.''' The maintenance manual calls the part in slot '''G2''' the ''controller card'', and IBM's glossary defines "controller" as "the microinstruction processor within the 5100 Portable Computer".<ref name="mim5100">IBM, ''IBM 5100 Maintenance Information Manual'', SY31-0405-3, October 1979 &mdash; hosted on this wiki as [[IBM 5100 Maintenance Information Manual]]. Section 2 item 209 (A1 board card locations and the 5100/5110 card jumpers); item 272 (Y1 socket pin assignments and the DC rail tolerance table). Section 4 "Theory" &mdash; Controller (15.1 MHz oscillator, 66.2 ns MCC pulses, I phase of three I cycles, E phase of one to five E cycles, the four program levels and their devices, sixteen two-byte registers per level addressable as the lowest 128 bytes of read/write storage) and Power (the supply described as a transistor switching regulator, its five DC rails, the overvoltage, undervoltage and overcurrent trip points, the +6 Vdc meter reference and the five-second restart rule). Section 5 "Circuits" logics 501 to 561, which name every A1 card by slot. Appendix B, 5100 specifications (dimensions, weight, heat output and power requirements). Appendix C, Microinstructions (the microinstruction set, the formats chart and the Control Command Data Table listing the 5100's I/O device addresses). Appendix D, Glossary.</ref> "PALM" is an IBM ''internal'' name that reached the public through the trade press and through IBM's own conference papers; both expansions in circulation &mdash; "Put All Logic in Microcode" and "Program All Logic in Microcode" &mdash; are attested, and the argument over them is set out on the [[IBM PALM processor]] page.

What IBM does publish about it:<ref name="mim5100" />

* A '''15.1 MHz oscillator''' generating '''66.2 ns''' multiclock-cycle (MCC) pulses.
* Every machine cycle is an '''I phase''' followed by an '''E phase'''. The I phase is always three I cycles &mdash; 3, 8 and 3 MCC pulses, so 14 MCC. The E phase is '''one to five E cycles''' of 3 or 8 MCC each, from 3 to 40 MCC depending on the op code.
* '''Four program levels''', each with sixteen two-byte registers that live physically on the processor card and are addressable as the lowest 128 bytes of read/write storage. Register 0 of each level is that level's instruction address register.
* Microinstructions are '''halfwords''' &mdash; two bytes &mdash; with the op code in the first four bits.

The often-quoted "1.9 MHz, 530 ns cycle" is not an IBM figure and is not a clock rate: 530 ns is eight MCC pulses (8 × 66.2 = 529.6 ns), which is the length of one 8-MCC cycle, not of a machine cycle. A complete microinstruction takes at least 14 + 3 = 17 MCC, or 1.13 µs.

IBM's own 1977 design paper describes the same processor as "'''a fast two-chip 8-bit processor'''" with '''49 16-bit microinstructions''' and four interrupt levels.<ref name="design77" /> That does not sit comfortably with the thirteen bipolar gate arrays visible on a real controller card, and the two accounts have not been reconciled; see [[IBM PALM processor]] for the evidence on both sides. The data path between the processor and storage is 16 bits plus 2 parity bits; the I/O path is 8 bits plus 1 parity bit.<ref name="design77" />

The processor directly addresses 64 KB through the storage address bus. The '''nonexecutable ROS is not in that address space at all''' &mdash; IBM attaches it through the I/O adapter, so it is read with a GET microinstruction as though it were a peripheral.<ref name="design77" /> That is why the language interpreters cannot be entered by a jump.