Editing IBM PALM processor (section)

== Architecture Summary ==

{| class="wikitable styled-table" style="width:70%;"
|+'''PALM architecture summary'''
! Parameter !! Value
|-
| Data path width || 16 bits (storage); 8 bits + parity (I/O)
|-
| Address bus width || 16 bits (64 KB directly addressable; bank-switching in microcode for larger configurations)
|-
| Storage Address Bus || 16 bits
|-
| Storage R/W Bus || 18 bits (16 data + 2 parity, one parity bit per byte)
|-
| I/O Data Bus || 8 bits + 1 parity, each direction (Bus In active-high; Bus Out active-low)
|-
| Master oscillator || 15.1 MHz on the processor card
|-
| Clock pulse || 66.2 ns
|-
| Machine cycle || 8 clock pulses ≈ 529.6 ns
|-
| Effective machine-cycle clock || ≈ 1.89 MHz
|-
| Average microinstruction time || ≈ 1.75 µs (per Roberson 1976; full per-instruction table at [[#Per-Instruction Timing (SY31-0405-3 Figure 11)|Per-Instruction Timing]] below)
|-
| Native instruction width || 16 bits (one "halfword")
|-
| General-purpose registers || 64 × 16-bit (16 registers per interrupt level × 4 interrupt levels); memory-mapped at $0000–$007F
|-
| Program Counter || R0 in each register bank (memory-mapped at offset 0 in the bank)
|-
| Link Register (IBM convention) || R1 in each bank — auto-loaded with PC+4 on a not-taken jump, enabling the IBM subroutine-call idiom
|-
| Interrupt levels || 4 (level 0 normal execution; level 1 communications; level 2 mass storage / printer / serial; level 3 keyboard); higher level = higher priority; switch is automatic at instruction boundaries
|-
| Process check || Parity error or invalid X/Y device address halts the processor and lights front-panel "PROCESS CHECK" lamp; jumper J2-S07 to J2-S09 on the 5110 (equivalent G2 pins on the 5100) can be removed to disable the halt for diagnostics
|}