Editing IBM PALM processor (section)

== Cycle Timing Reconciled ==

[[File:PALM clock cycles.gif|right|thumb|320px|PALM clock-cycle structure: each machine cycle is built from 8 clock pulses of 66.2 ns each (529.6 ns total). An instruction phase takes 3 cycles; an execution phase takes 1–3 cycles depending on the instruction. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]

The widely-quoted figures "1.9 MHz" and "530 ns cycle" are reconciled by the underlying clock hierarchy:

* The processor card carries a '''15.1 MHz''' master oscillator.
* Each clock pulse is '''66.2 ns''' wide.
* A '''machine cycle''' consists of '''eight''' clock pulses: 8 × 66.2 ns = '''529.6 ns''' ≈ 530 ns.
* The effective machine-cycle clock is therefore '''1 / 529.6 ns''' ≈ '''1.89 MHz''' — rounded to "1.9 MHz" in most secondary sources.

A native PALM instruction takes one '''instruction phase''' (3 machine cycles) plus one '''execution phase''' (1–3 machine cycles depending on the instruction). The instruction phase loads the Storage Address Register from R0 (the program counter), fetches the instruction into the Operation Register, then increments R0 by 2. The execution phase performs the ALU operation, register write-back, or I/O transfer. The 1.75 µs "average microinstruction time" quoted by Roberson 1976 corresponds to a 3-cycle instruction; longer instructions reach ~2.6 µs.