PLA Replacement Options: Difference between revisions
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Created page with "The original '''MOS 906114-01 Programmable Logic Array (PLA)''' in early C64 board revisions (ASSY 326298 → 250466) is _the_ single highest-failure-rate part in the machine. It runs hot (≈ 65 °C surface on an un-ventilated bread-bin), consumes ≈ 120 mA, and any internal electrical overstress manifests as: * '''Black screen / no border''' on power-up. * Colour-flashing “garbage” that crashes after warm-up. * Selective cartridge or bank-switch errors (E..." |
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Because original spare parts are scarce and almost forty years old, several replacement families have appeared. They differ in technology, power draw, compatibility and cost. | Because original spare parts are scarce and almost forty years old, several replacement families have appeared. They differ in technology, power draw, compatibility and cost. | ||
== | == Selection criteria == | ||
{| class="wikitable" | {| class="wikitable" | ||
! Criterion !! Why it matters | ! Criterion !! Why it matters | ||
| Line 21: | Line 21: | ||
|} | |} | ||
== | == Replacement families == | ||
=== 1. Salvaged original MOS ceramic PLAs === | === 1. Salvaged original MOS ceramic PLAs === | ||
* Perfect electrical fit if tested good, but still run hot and may fail again. | * Perfect electrical fit if tested good, but still run hot and may fail again. | ||
| Line 54: | Line 54: | ||
* Excellent edge-rate but enormous current draw; avoided except as teaching tools. | * Excellent edge-rate but enormous current draw; avoided except as teaching tools. | ||
== | == Installation == | ||
# Power off & unplug PSU; discharge by pressing the power switch several times. | # Power off & unplug PSU; discharge by pressing the power switch several times. | ||
# Gently remove the original PLA from socket '''U17''' using a PLCC puller or flat tool. | # Gently remove the original PLA from socket '''U17''' using a PLCC puller or flat tool. | ||
| Line 64: | Line 64: | ||
## Run a fast-loader cartridge or *Dead Test* to exercise all decode paths. | ## Run a fast-loader cartridge or *Dead Test* to exercise all decode paths. | ||
== | == Comparison summary == | ||
{| class="wikitable" | {| class="wikitable" | ||
! Solution !! Cost !! Heat !! Cartridge compat. !! Availability | ! Solution !! Cost !! Heat !! Cartridge compat. !! Availability | ||
|- | |- | ||
| Salvaged MOS || High || 🔥🔥🔥 || ✅ || declining | | Salvaged MOS || High || 🔥🔥🔥 || ✅ || declining | ||
|- | |||
| EPROM TTL || Low || 🔥🔥 || ⚠️ mixed || DIY only | | EPROM TTL || Low || 🔥🔥 || ⚠️ mixed || DIY only | ||
|- | |||
| GAL20V8 || Low-mid || 🔥 || ✅ || open-source | | GAL20V8 || Low-mid || 🔥 || ✅ || open-source | ||
|- | |||
| CPLD/FPGA (e.g. PLAnkton) || Mid (15–25 €) || ❄️ || ✅✅✅ || multiple stores | | CPLD/FPGA (e.g. PLAnkton) || Mid (15–25 €) || ❄️ || ✅✅✅ || multiple stores | ||
|- | |||
| TTL array || High (parts) || 🔥🔥🔥 || ✅ || niche | | TTL array || High (parts) || 🔥🔥🔥 || ✅ || niche | ||
|} | |} | ||
== | == Further reading == | ||
* Raymond Carlsen, “PLA Failures and Substitutes” | * Raymond Carlsen, “PLA Failures and Substitutes” | ||
[[Category:Commodore 64 Modifications and Enhancements]] | [[Category:Commodore 64 Modifications and Enhancements]] | ||
[[Category:Commodore Systems]] | [[Category:Commodore Systems]] | ||
Latest revision as of 14:39, 22 January 2026
The original MOS 906114-01 Programmable Logic Array (PLA) in early C64 board revisions (ASSY 326298 → 250466) is _the_ single highest-failure-rate part in the machine. It runs hot (≈ 65 °C surface on an un-ventilated bread-bin), consumes ≈ 120 mA, and any internal electrical overstress manifests as:
- Black screen / no border on power-up.
- Colour-flashing “garbage” that crashes after warm-up.
- Selective cartridge or bank-switch errors (EXROM/GAME decoding faults).
Because original spare parts are scarce and almost forty years old, several replacement families have appeared. They differ in technology, power draw, compatibility and cost.
Selection criteria
[edit | edit source]| Criterion | Why it matters |
|---|---|
| Timing accuracy | PLA outputs must meet a < 60 ns access window to avoid VIC-II bus contention; marginal parts work in BASIC but fail with fast cartridges. |
| Voltage tolerance & heat | Lower idle current (≤ 20 mA) keeps internal case temperature down and avoids over-loading the 5 V rail. PLAnkton, for example, dissipates < 0.2 W compared with ≈ 0.6 W for the ceramic MOS part. |
| Board compatibility | 250469 “short-board” machines integrate the PLA inside the 251715-01 gate-array; external plug-ins are not required there. |
| Cartridge support | Fast loaders (Epyx FastLoad, KFF, EasyFlash) depend on tight /CASRAM and /ROML asserts — earlier EPROM-based substitutes can break these. |
Replacement families
[edit | edit source]1. Salvaged original MOS ceramic PLAs
[edit | edit source]- Perfect electrical fit if tested good, but still run hot and may fail again.
- Short supply & rising price (US $40–80 on auction sites).
2. EPROM + TTL glue (first-generation DIY)
[edit | edit source]- EPROM (27C512/27C256) programmed with PLA truth-table, gated by 74LS04/74LS86.
- Cheap but slow output edges and ~65 mA current → will over-heat inside a closed case.
- Timing marginal with some Ocean/AR II cartridges.
3. GAL / PAL-based (PLA20V8, ThED PLA20V8, “128 PLA in C64”)
[edit | edit source]- Single GAL20V8 or ATF22V10C, pin-compatible.
- Draw ≈ 20 mA, emit little heat.
- Open-source JEDEC; hobbyists can burn their own chips.
- Slightly higher propagation delay than CPLD, but passes timing on > 99 % of boards in field reports.
4. CPLD / FPGA-based (current gold standard)
[edit | edit source]| Replacement | Logic core | Idle current | Notable points |
|---|---|---|---|
| SuperPLA V3 | Xilinx XC9536XL | ≈ 15 mA | Earliest “plug-and-play” commercial part, wide PAL/NTSC & cartridge compatibility. 20 € PCB kit. |
| U17 PLAnkton | Altera MAX CPLD | < 10 mA | Eight-layer µPCB nestled inside a plastic SIL socket; runs cool & supports C16/+4 PLAs via jumper. |
| RealPLA / “Ultimate PLA” | Lattice ispMACH 4064 | 12 mA | Shipped with _Ultimate-64_ boards; cartridge timing verified with Kung-Fu Flash & Epyx. |
| SaRuMan-64 | iCE40LP384 FPGA | ~ 8 mA | Adds a tiny linear-drop regulator to isolate noisy 5 V rails; user-upgradable bit-stream. |
5. Multi-chip TTL recreations (educational)
[edit | edit source]- 27 × 74LS/AHC gates that implement the PLA equations.
- Excellent edge-rate but enormous current draw; avoided except as teaching tools.
Installation
[edit | edit source]- Power off & unplug PSU; discharge by pressing the power switch several times.
- Gently remove the original PLA from socket U17 using a PLCC puller or flat tool.
- Visually inspect the socket for oxidation or lifted pads.
- Align the notch or pin-1 indicator on the replacement with the board silk.
- Firmly press straight down — do not rock side-to-side.
- Power on and test:
- BASIC screen appears → `PRINT FRE(0)` returns 38911.
- Run a fast-loader cartridge or *Dead Test* to exercise all decode paths.
Comparison summary
[edit | edit source]| Solution | Cost | Heat | Cartridge compat. | Availability |
|---|---|---|---|---|
| Salvaged MOS | High | 🔥🔥🔥 | ✅ | declining |
| EPROM TTL | Low | 🔥🔥 | ⚠️ mixed | DIY only |
| GAL20V8 | Low-mid | 🔥 | ✅ | open-source |
| CPLD/FPGA (e.g. PLAnkton) | Mid (15–25 €) | ❄️ | ✅✅✅ | multiple stores |
| TTL array | High (parts) | 🔥🔥🔥 | ✅ | niche |
Further reading
[edit | edit source]- Raymond Carlsen, “PLA Failures and Substitutes”