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IBM PALM processor: Difference between revisions

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Deep technical page on the IBM PALM processor — verified facts only with honest documentation gaps
 
Replace infobox photo with actual PALM card (J2 controller); add Identified ICs section with all 13 gate array part numbers transcribed; embed Stuttgart data-flow, clock-cycle, RWS memory map, and SAR bits diagrams
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{{Infobox computer hardware
{{Infobox computer hardware
| name            = IBM PALM
| name            = IBM PALM
| image            = [[File:IBM 5100 overhead view.jpg|260px]]
| image            = [[File:PALM J2 controller card big.jpg|260px]]
| caption          = Top-down view inside an IBM 5100; the PALM controller card is the processor module that sits on the A1 backplane alongside ROS, RAM and I/O cards (image: Wikimedia Commons, public domain).
| caption          = The IBM PALM controller card (Card J2) — all 13 bipolar "Dutchess" gate arrays in metal-can packages are visible, with the central round metal-can oscillator and three small DIP devices in the upper-middle region. (Photograph: Christian Corti, Stuttgart Computer Museum, ©1999–2017, used with attribution.)
| developer        = IBM General Systems Division, Boca Raton, Florida — "PALM Development Group" led by Roger Abernathy
| developer        = IBM General Systems Division, Boca Raton, Florida — "PALM Development Group" led by Roger Abernathy
| manufacturer    = IBM
| manufacturer    = IBM
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== Cycle Timing Reconciled ==
== Cycle Timing Reconciled ==
[[File:PALM clock cycles.gif|right|thumb|320px|PALM clock-cycle structure: each machine cycle is built from 8 clock pulses of 66.2 ns each (529.6 ns total). An instruction phase takes 3 cycles; an execution phase takes 1–3 cycles depending on the instruction. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]


The widely-quoted figures "1.9 MHz" and "530 ns cycle" are reconciled by the underlying clock hierarchy:
The widely-quoted figures "1.9 MHz" and "530 ns cycle" are reconciled by the underlying clock hierarchy:
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== Bus and Memory Map ==
== Bus and Memory Map ==
[[File:PALM RWS memory map.gif|right|thumb|320px|RWS (Read-Write Storage) memory map of the IBM 5110 as seen by PALM. The first 128 bytes are the memory-mapped register-bank window; the remaining RWS is general-purpose RAM. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]
[[File:PALM SAR bits.gif|right|thumb|320px|Storage Address Register (SAR) bit-field layout. (Diagram: Christian Corti, Stuttgart Computer Museum.)]]


PALM uses '''three physically separate buses''' on the A1 backplane:
PALM uses '''three physically separate buses''' on the A1 backplane:
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[[File:IBM 5100 overhead view.jpg|right|thumb|320px|IBM 5100 chassis interior — the PALM card mounts on the A1 backplane alongside ROS, RWS and I/O cards. The PALM card carries 13 bipolar gate arrays in metal cans on a single multi-layer PCB. Image: Wikimedia Commons, public domain.]]
[[File:IBM 5100 overhead view.jpg|right|thumb|320px|IBM 5100 chassis interior — the PALM card mounts on the A1 backplane alongside ROS, RWS and I/O cards. The PALM card carries 13 bipolar gate arrays in metal cans on a single multi-layer PCB. Image: Wikimedia Commons, public domain.]]
=== Identified ICs on the PALM Board ===
The 13 Dutchess gate arrays are visible and labelled with IBM part numbers in Christian Corti's high-resolution photograph of the J2 controller card. The IBM part-number format on this generation of Dutchess parts is '''aaaaaa IBM ''nn''''' where '''aaaaaa''' is a 7-digit IBM part number identifying the specific personalisation of the masterslice, and '''nn''' is the IBM family designator (here, '''22''' — denoting the Dutchess family in this configuration). A second line gives a date / lot code in the form '''1-yyy nnnn''' where '''yyy''' appears to be a 3-digit week-of-fab code and '''nnnn''' a serial sequence.
The following IC identifications are transcribed directly from the J2 card photograph. Identification of '''which logical function''' each part performs (ALU, register file, microcode sequencer, etc.) is documented in IBM's SY31-0405 (5100 MIM) and SY34-0193 (5120 CSLM) — but cannot be derived from the photograph alone, and is listed below as '''not yet mapped'''.
{| class="wikitable styled-table" style="width:100%;"
|+'''Identified ICs on the PALM (Card J2) controller card'''
! Position (row, col) !! IBM part number !! Family !! Date / lot code !! Logical function (from CSLM) !! Notes
|-
| 1, 1 (top-left) || '''2706597''' || IBM 22 || 1-841 1062 || Not yet mapped || Same part also at position 4, 1
|-
| 1, 3 (top-right) || '''1554466''' || IBM 22 || 1-849 2247 || Not yet mapped ||
|-
| 2, 1 || '''5564251''' || IBM 22 || 1-849 2865 || Not yet mapped || Same part also at position 3, 1
|-
| 2, 3 || '''2706506''' || IBM 22 || 1-842 1304 || Not yet mapped ||
|-
| 3, 1 || '''5564251''' || IBM 22 || 1-849 2865 || Not yet mapped ||
|-
| 3, 2 (centre) || '''1554469''' || IBM 22 || 1-849 2746 || Not yet mapped ||
|-
| 3, 3 || '''5564255''' || IBM 22 || 1-839 0937 || Not yet mapped ||
|-
| 4, 1 || '''2706597''' || IBM 22 || 1-847 2327 || Not yet mapped ||
|-
| 4, 2 || '''2706503''' || IBM 22 || 1-839 0923 || Not yet mapped ||
|-
| 4, 3 || '''1554468''' || IBM 22 || 1-849 2631 || Not yet mapped ||
|-
| 5, 1 (bottom-left) || '''1554470''' || IBM 22 || 1-844 6469 || Not yet mapped ||
|-
| 5, 2 || '''2706505''' || IBM 22 || 1-842 1516 || Not yet mapped ||
|-
| 5, 3 (bottom-right) || '''1554467''' || IBM 22 || 1-843 1454 || Not yet mapped ||
|}
That gives '''13 Dutchess gate arrays''' (with two repeats — '''2706597''' appears twice and '''5564251''' appears twice — leaving '''11 unique masterslice personalisations''' across the 13 sockets). The repeats are consistent with multiple functions implemented from the same masterslice metal-mask design (the same gate array used twice for byte-paired data paths, for example).
==== Other identified board devices ====
Three smaller devices are visible in the upper-middle region of the J2 card, between the row-1 and row-2 Dutchess arrays. These are the '''3 conventional TTL DIPs''' referenced by Wikipedia and PC Magazine.
{| class="wikitable styled-table" style="width:100%;"
|+'''Smaller ICs on the PALM board (transcribed from the J2 card photograph)'''
! Position !! Marking !! Device type !! Notes
|-
| Upper-middle, left || '''210086-C''', LC 7676.20, 7828 CT || Small DIP || Function not identified from photograph alone
|-
| Upper-middle, right || '''M-210086-C''', LC 7676/20, 7825 2 CT || Small DIP || Same base part number as above; "M-" prefix variant
|-
| Top-centre (green-marked) || Round metal-can with green dot indicator || Crystal oscillator can || Most plausibly the '''15.1 MHz master oscillator''' that produces the 66.2 ns clock pulse. The green dot is consistent with an IBM marking convention for tuned / specified crystals
|}
The "210086-C" and "M-210086-C" markings appear on small DIPs with date codes 7825 / 7828 (the 25th and 28th week of 1978), which is consistent with this specific J2 card being from a 1978 5110 — the date codes are slightly later than the row-1 gate array codes (which include weeks 841, 842, 843, 844, 847, 849 of 1978 by the "1-yyy" convention).
The Stuttgart photograph also shows a board edge marking '''16078496458VG41''' (probably an IBM card serial / FRU number) and additional small surface-mount components and decoupling capacitors near the right edge of the board.
==== Reading the IBM 22 family designator ====
The '''IBM 22''' family designator on every Dutchess part on this card is consistent across the entire 13-IC complement, confirming they are all the same masterslice variant. Different metal-mask personalisations produce the different 7-digit base part numbers (2706597, 1554466, 5564251, 2706506, 1554469, 5564255, 2706503, 1554468, 1554470, 2706505, 1554467) but the underlying silicon is the same Dutchess wafer.
The Dutchess gate count (~134 logic gates per chip) and the 13-chip board complement therefore give the PALM processor an effective gate count of approximately '''13 × 134 ≈ 1,740 logic gates of bipolar Schottky-TTL logic''' — comparable in raw gate count to the early-generation single-chip CPUs of the same era (Intel 8080 ≈ 4,500 transistors / equivalent to a few hundred gates; PALM has more gates but spread across 13 packages).


=== Function Blocks of PALM ===
=== Function Blocks of PALM ===
[[File:PALM dataflow.gif|center|thumb|640px|Data-flow diagram of the IBM PALM processor reverse-engineered by Christian Corti from an actual 5110 controller card. Shows the Read Data Register (RDR), Storage Address Register (SAR), Operation Register, Storage Data Register (SDR), the 8-bit-wide Arithmetic Logic Unit, the Control ROS Unit, the four-banked register file, and the connections to the three external buses (Storage Address Bus, Storage R/W Bus, and I/O Data Bus). (Diagram: Christian Corti, Stuttgart Computer Museum, ©1999–2017, used with attribution.)]]


The Stuttgart Computer Museum's reverse-engineered data-flow diagram of the PALM module identifies the following logical function blocks. The exact one-to-one mapping of these blocks onto the 13 Dutchess gate arrays is documented in IBM's '''SY31-0405 Maintenance Information Manual''' (5100) and '''SY34-0193 Computing System Logic Manual''' (5120) — but is not extracted in any widely-mirrored secondary source. Restorers needing this mapping must consult those PDFs directly.
The Stuttgart Computer Museum's reverse-engineered data-flow diagram of the PALM module identifies the following logical function blocks. The exact one-to-one mapping of these blocks onto the 13 Dutchess gate arrays is documented in IBM's '''SY31-0405 Maintenance Information Manual''' (5100) and '''SY34-0193 Computing System Logic Manual''' (5120) — but is not extracted in any widely-mirrored secondary source. Restorers needing this mapping must consult those PDFs directly.
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This article documents PALM at the level supported by publicly available sources. The following details are '''documented in IBM's CE manuals but not in any widely-mirrored secondary source''', and are listed as gaps for future research:
This article documents PALM at the level supported by publicly available sources. The following details are '''documented in IBM's CE manuals but not in any widely-mirrored secondary source''', and are listed as gaps for future research:


# '''The one-to-one mapping of the 13 Dutchess gate arrays onto the PALM function blocks.''' Documented in IBM 5100 MIM SY31-0405 (PALM appendix) and IBM 5120 CSLM SY34-0193 — but not transcribed into any community-accessible secondary source.
# '''The one-to-one mapping of the 13 Dutchess gate arrays onto the PALM function blocks.''' The IBM part numbers for all 13 gate arrays are now identified on this page (see [[#Identified ICs on the PALM Board|"Identified ICs on the PALM Board"]] above), but '''which function each part implements''' (ALU, register file, microcode sequencer, bus interface, etc.) is documented only in IBM 5100 MIM SY31-0405 (PALM appendix) and IBM 5120 CSLM SY34-0193, and has not been transcribed into any community-accessible secondary source.
# '''The identity (manufacturer / part number) of the 3 TTL DIPs and 1 round metal-can device on the PALM board.''' High-resolution photos of the J2 card (e.g. at the Stuttgart Computer Museum) would allow identification by silkscreen, but no source has done this systematically.
# '''The function (not just the part number) of the 3 TTL DIPs and 1 round metal-can device on the PALM board.''' The part numbers '''210086-C''' / '''M-210086-C''' for the small DIPs and the visual identification of the round metal can as a crystal-oscillator can are now recorded here. The exact role of the 210086-C devices in the PALM design is documented in the CSLM but not in any secondary source.
# '''The exact System/370 instruction subset emulated by PALM microcode.''' IBM did not publish this; the manuals deliberately omit the emulation layer.
# '''The exact System/370 instruction subset emulated by PALM microcode.''' IBM did not publish this; the manuals deliberately omit the emulation layer.
# '''Die-shot or photomicrograph of a Dutchess masterslice.''' No publicly available example.
# '''Die-shot or photomicrograph of a Dutchess masterslice.''' No publicly available example.
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