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Replace infobox photo with actual PALM card (J2 controller); add Identified ICs section with all 13 gate array part numbers transcribed; embed Stuttgart data-flow, clock-cycle, RWS memory map, and SAR bits diagrams
Major rewrite: corrected S/370 -> S/360 emulator (per direct disassembly evidence); added IBM Chapter 2 full mnemonics; per-instruction timing table from SY31-0405 Figure 11; GETA priority encoder section; no-stack/no-branch architectural note; PALM self-hosting via GENASM 1977; 5100 card complement table; memory map; ROS extraction methodology; removed Significance section per request
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| introduced      = 1973 (in the SCAMP prototype); 1975 in the first production machine, the [[IBM 5100]]
| introduced      = 1973 (in the SCAMP prototype); 1975 in the first production machine, the [[IBM 5100]]
| discontinued    = c. 1982 (last production machine, the [[IBM 5120]], withdrawn 10 December 1982)
| discontinued    = c. 1982 (last production machine, the [[IBM 5120]], withdrawn 10 December 1982)
| arch            = Proprietary 16-bit microcoded architecture with four interrupt levels and 64 general-purpose registers (16 × 4 banks)
| arch            = Proprietary 16-bit microcoded architecture; 8-bit ALU; four interrupt levels each with its own bank of 16 general-purpose 16-bit registers (64 architectural registers visible to the programmer simultaneously); no hardware stack; no conditional branch — all conditional flow is test-and-skip
| data_width      = 16 bits (storage); 8 bits + parity (I/O)
| data_width      = 16-bit register file and ISA; '''8-bit ALU'''; 18-bit Storage Read/Write Bus (16 data + 2 parity); 9-bit I/O bus each direction (8 data + 1 parity)
| address_width    = 16 bits (64 KB direct); bank-switching extends in microcode
| address_width    = 16-bit Storage Address Bus (64 KB byte-addressed); SAB bit 0 = card-select between the two executable-ROS cards giving 128 KB executable-code addressing; bank-switching in microcode for larger configurations
| clock            = 15.1 MHz master oscillator → 66.2 ns clock pulse → eight pulses per machine cycle → ≈ 1.89 MHz effective machine-cycle clock; ≈ 530 ns per machine cycle; ≈ 1.75 µs average microinstruction execution time
| clock            = 15.1 MHz crystal oscillator producing 66.2 ns "MCC" (multiclock cycle) pulses on the controller card. Per-instruction cycle composition: '''I-phase = 14 MCC fixed''' (3 + 8 + 3); '''E-phase = 1–5 E-cycles''' of 3 or 8 MCC each, up to 40 MCC maximum. Typical native instruction throughput 1.13–5.30 µs from RWS, 1.13–2.05 µs from ROS (per SY31-0405-3 Figure 11)
| transistors      = 13 bipolar "Dutchess" masterslice gate arrays in square metal cans, each carrying ~134 logic gates of Schottky-TTL-compatible bipolar silicon
| transistors      = 13 bipolar "Dutchess" masterslice gate arrays in square metal cans, each carrying ~134 logic gates of Schottky-TTL-compatible bipolar silicon
| package          = Multi-board controller card (not a single chip) — 13 × metal-can gate arrays + 3 × TTL DIPs + 1 × round metal-can device on a single multi-layer PCB with gold-plated edge connector
| package          = Multi-board controller card (not a single chip) — 13 × metal-can gate arrays + 3 × TTL DIPs + 1 × round metal-can device on a single multi-layer PCB with gold-plated edge connector
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}}
}}


The '''IBM PALM''' is a 16-bit board-level microprocessor designed and built by IBM General Systems Division at Boca Raton, Florida, in the early 1970s. PALM is built from 13 '''bipolar masterslice gate arrays''' on a single PCB — '''it is not a single integrated circuit''' but a complete processor module sometimes called by IBM itself "the controller" rather than "the processor". PALM was used in the [[IBM 5100]] Portable Computer (1975), the [[IBM 5110]] Computing System (1978), and the [[IBM 5120]] Computing System (1980).
The '''IBM PALM''' is a 16-bit board-level microprocessor designed and built by IBM General Systems Division at Boca Raton, Florida, in the early 1970s. PALM is built from 13 '''bipolar masterslice gate arrays''' on a single PCB — '''it is not a single integrated circuit''' but a complete processor module that IBM's own public-facing documentation refers to only as "the controller" (the term "PALM" never appears in IBM's customer-facing manuals for the 5100, 5110 or 5120). PALM was used in the [[IBM 5100]] Portable Computer (1975), the [[IBM 5110]] Computing System (1978), and the [[IBM 5120]] Computing System (1980).


The PALM architecture is unusual in that it executes a narrow native 16-bit instruction set in hardware, and uses '''microcode interpretation''' to run higher-level instruction sets — including '''emulators of subsets of the IBM System/360, System/370 and System/3''' instruction sets — so that the unmodified APLSV interpreter (from System/370 APL) and the System/3 Model 6 BASIC interpreter can run on the 5100 family in their original binary form. This emulation capability is what gives the 5100 its later notoriety in the [[IBM 5100#In Popular Culture: The John Titor Story|John Titor]] Internet folklore.
The PALM architecture is unusual in that it executes a narrow native 16-bit instruction set in hardware, and uses higher-level interpreter ROS to run instruction sets from other IBM machines:
 
* The '''APL''' environment runs on top of an '''IBM System/360 emulator''' written in PALM microcode in the executable ROS, which then executes the APL interpreter from the non-executable language ROS in '''System/360 object code'''. This was confirmed by direct disassembly of the APL executable ROS — only S/360 opcodes appear in the dispatch, no S/370-specific instructions.<ref>Corti, C., Stuttgart Computer Museum, IBM 5110 emulator notes (`aplros.asm` disassembly).</ref><ref>voidstar.blog (Brett W. Hill), IBM 5100 executive-ROS extraction project — annotated APL ROS disassembly.</ref>
* The '''BASIC''' environment runs on top of a '''separate''' microcode interpreter that emulates the '''IBM System/3 Model 6''' instruction subset; the BASIC interpreter is itself System/3 object code from System/3 BASIC.
 
The S/360 emulator is therefore '''APL-only'''. BASIC uses the System/3 emulator. IBM did not disclose either emulator in the customer documentation; the existence of the S/360 emulator is documented only by reverse engineering of the executable ROS (Corti and Stepleton 2007–2019) and by IBM engineers' later off-the-record confirmations in the alt.folklore.computers archives. This is the source of the [[IBM 5100#In Popular Culture: The John Titor Story|John Titor]] folklore — the claim "the 5100 secretly contained a System/360 emulator" turns out to be substantively true at the architectural level.


== Name and Acronym Expansion ==
== Name and Acronym Expansion ==
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Both forms appear in IBM-originated documentation. The 5100 development team in Boca Raton appears to have used "Put"; the formal IEEE paper used "Program". This page records both rather than picking one.<ref>Friedl, P. J. "SCAMP: The Missing Link In The PC's Past?" PC Magazine 2(6): 190–197, November 1983.</ref><ref>Roberson, D. A. "A Microprocessor-based portable computer: The IBM 5100." Proceedings of the IEEE 64(6): 994–999, June 1976.</ref>
Both forms appear in IBM-originated documentation. The 5100 development team in Boca Raton appears to have used "Put"; the formal IEEE paper used "Program". This page records both rather than picking one.<ref>Friedl, P. J. "SCAMP: The Missing Link In The PC's Past?" PC Magazine 2(6): 190–197, November 1983.</ref><ref>Roberson, D. A. "A Microprocessor-based portable computer: The IBM 5100." Proceedings of the IEEE 64(6): 994–999, June 1976.</ref>
=== First Public IBM Use of the Term "PALM" ===
The earliest publicly accessible IBM document using the term "PALM" is the '''GENASM PALM''' manual by H. J. Myers (1977, IBM Internal Use Only). GENASM was IBM's macro-assembler generator for the PALM target machine; "PALM" in the title refers to file index 6 on the GENASM distribution tape (the PALM target-machine definition file).<ref>Myers, H. J., ''GENASM PALM'' (IBM Internal Use Only, 1977). Mirror at voidstar.blog GitHub `voidstar78/IBM_5100_DOCS/PDFs_5100/AssemblerGenerator.pdf`.</ref>
'''No public-facing IBM manual from the 5100 / 5110 / 5120 product line uses the term "PALM"''' — not the 5100 Maintenance Information Manual (SY31-0405), not the 5110 MIM (SY31-0550), not the 5120 Computing System Logic Manual (SY34-0193), and not the user-language reference manuals. IBM's customer-facing terminology is always "the controller" (the card in slot G2 on the 5100 / J2 on the 5110). The word "PALM" was internal-only until the late-1980s / 1990s, when it leaked into the IBM Archives and the Roberson IEEE-Proceedings paper retrospectively associated it with the controller architecture.


== Origin: SCAMP, 1973 ==
== Origin: SCAMP, 1973 ==
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| Effective machine-cycle clock || ≈ 1.89 MHz
| Effective machine-cycle clock || ≈ 1.89 MHz
|-
|-
| Average microinstruction time || ≈ 1.75 µs (per Roberson 1976)
| Average microinstruction time || ≈ 1.75 µs (per Roberson 1976; full per-instruction table at [[#Per-Instruction Timing (SY31-0405-3 Figure 11)|Per-Instruction Timing]] below)
|-
|-
| Native instruction width || 16 bits (one "halfword")
| Native instruction width || 16 bits (one "halfword")
|-
|-
| General-purpose registers || 64 × 16-bit (16 registers per interrupt level × 4 interrupt levels)
| General-purpose registers || 64 × 16-bit (16 registers per interrupt level × 4 interrupt levels); memory-mapped at $0000–$007F
|-
|-
| Program Counter || R0 in each register bank (memory-mapped at offset 0 in the bank)
| Program Counter || R0 in each register bank (memory-mapped at offset 0 in the bank)
|-
|-
| Interrupt levels || 4 (level 0 normal execution; level 1 communications; level 2 mass storage / printer / serial; level 3 keyboard)
| Link Register (IBM convention) || R1 in each bank — auto-loaded with PC+4 on a not-taken jump, enabling the IBM subroutine-call idiom
|-
|-
| Control ROS (on PALM module) || 256 × 32-bit microcode store
| Interrupt levels || 4 (level 0 normal execution; level 1 communications; level 2 mass storage / printer / serial; level 3 keyboard); higher level = higher priority; switch is automatic at instruction boundaries
|-
|-
| Executable ROS (off-PALM) || ~16K × 18-bit per language (16K × 18 for BASIC; another 16K × 18 for APL)
| Process check || Parity error or invalid X/Y device address halts the processor and lights front-panel "PROCESS CHECK" lamp; jumper J2-S07 to J2-S09 on the 5110 (equivalent G2 pins on the 5100) can be removed to disable the halt for diagnostics
|-
| Process check || Parity error or invalid X/Y device address halts the processor and lights front-panel "PROCESS CHECK" lamp (unless an interlock jumper is removed)
|}
|}


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|}
|}


This table is reconstructed by the Stuttgart Computer Museum from a recovered IBM-internal "Chapter 2" PALM machine-language document held by the IBM Museum in Sindelfingen.<ref>Corti, C. Stuttgart Computer Museum IBM 5110 hardware pages, http://computermuseum.informatik.uni-stuttgart.de/dev/ibm_5110/technik/en/ — "Opcodes" section.</ref>
This top-nibble table is reconstructed by the Stuttgart Computer Museum from a recovered IBM-internal "Chapter 2" PALM machine-language document held by the IBM Museum in Sindelfingen, cross-referenced with '''Appendix C of the SY31-0405 5100 Maintenance Information Manual''' (which contains the same opcode set with abbreviated descriptions, and which was '''omitted''' from the 5110 MIM SY31-0550).<ref>Corti, C. Stuttgart Computer Museum IBM 5110 hardware pages, "Opcodes" section.</ref><ref>IBM. ''IBM 5100 Maintenance Information Manual'' SY31-0405-3, October 1979, Appendix C "Microinstructions".</ref>
 
=== IBM Chapter 2 Mnemonics (Full Detail) ===
 
The IBM internal "Chapter 2" microinstruction reference (transcribed in full by Corti at the Stuttgart Computer Museum) and SY31-0405-3 Appendix C together document every native PALM opcode with IBM's own mnemonics. The encoding pattern: all instructions are 16-bit halfwords; the top 4 bits select the opcode class; opcode '''0''' is overloaded — the low 4 bits of byte 0 (the "AM modifier") select one of 16 ALU / move / halfword operations.
 
{| class="wikitable styled-table" style="width:100%;"
|+'''IBM Chapter 2 native PALM microinstruction set (SY31-0405-3 Appendix C / IBM Sindelfingen Chapter 2)'''
! Opcode pattern !! IBM mnemonic !! Function
|-
| '''0xy0–4''' || '''MVM2 / MVM1 / MVP1 / MVP2 / MOVE''' || Move halfword (with optional pre-decrement / pre-increment of ±1 or ±2 on the source pointer)
|-
| '''0xy5–7''' || '''AND / ORB / XOR''' || 8-bit logical operations on the low byte
|-
| '''0xy8 / 0xy9''' || '''ADD / SUB''' || 8-bit arithmetic with carry / borrow propagation into the high byte
|-
| '''0xyA / 0xyB''' || '''ADDS1 / ADDS2''' || "Add special" — multi-byte carry / borrow propagation for synthesised wider arithmetic
|-
| '''0xyC / 0xyD''' || '''HTL / LTH''' || Byte swap — High-to-Low / Low-to-High within a register
|-
| '''0xyE / 0xyF''' || '''GETR / GETA''' || I/O get-to-register; '''GETA''' performs an 8-way priority decode of Bus In bits to add 0 / 2 / 4 / 6 / 8 / A / C / E to the destination — see ''GETA priority encoder'' below
|-
| '''1ijj''' || '''CTL''' || I/O control command (sends a control byte to a device)
|-
| '''2xii / 3xii''' || '''LDHD / STHD''' || Direct halfword load / store — direct addresses are limited to the first 256 halfwords (the page-0 region)
|-
| '''4ix?''' || '''PUTB''' || I/O put-byte, with auto-modification of an indirect register if specified
|-
| '''5xy? / 7xy?''' || '''STHI / STBI''' || Indirect store, halfword / byte (uses Ry as pointer with optional pre/post inc/dec)
|-
| '''6xy? / Dxy?''' || '''LDBI / LDHI''' || Indirect load, byte / halfword
|-
| '''8xii''' || '''EMIT''' || Load 8-bit immediate into the low byte of register Rx
|-
| '''9xii''' || '''CLRI''' || Clear bits via 8-bit mask (logical AND-NOT immediate)
|-
| '''Axii''' || '''ADDI''' || Add 8-bit immediate '''with implicit +1''' (so ADDI 0x00 adds 1, ADDI 0xFF adds 256)
|-
| '''Bxii''' || '''SETI''' || Set bits via 8-bit mask (logical OR immediate)
|-
| '''Cxy?''' || '''JLE / JLO / JEQ / JNO / JALL / JALLM / JNOM / JHAM / JHI / JHE / JHL / JSB / JSN / JSNM / JSM / JHSNM''' || Test-and-skip family. Modifier bits 8–F flip each test to its "skip-on-false" variant. There are no real jumps — all flow control is built from these conditional skips
|-
| '''E0x?''' || '''SHFTR / ROTR''' || Shift / rotate the low byte (rotate-by-4 = nibble swap; rotate-by-3, -1 also encodable)
|-
| '''Eix?''' || '''GETB / GETRB''' || I/O byte fetch / status fetch
|-
| '''Fxii''' || '''SUBI''' || Subtract 8-bit immediate '''with implicit −1''' (so SUBI 0x00 subtracts 1)
|}
 
=== No Hardware Stack, No Conditional Branch ===
 
PALM has '''no PUSH / POP, no CALL / RET, no JMP / Bcc''' in its native instruction set. All flow control is built from:
 
* '''Conditional skip''' (opcode group C) — skips the next halfword if the test passes.
* '''Direct write to R0''' (the program counter / IAR) — by `MOVE R0, Rx`, `LDHI R0, *(Ry)`, or `ADDI R0, imm` / `SUBI R0, imm`.
 
Subroutine calls are an IBM idiom: increment R0 by 2 into a "link register" (any register the programmer designates — R1 by IBM convention) to capture the return address, then overwrite R0 with the call target. Return is `MOVE R0, R1`. Recursive or nested calls require the programmer to build their own stack in RWS — there is no hardware stack pointer.
 
This skip-and-write model is uncommon among 1970s ISAs and reflects PALM's strict role as a microcode interpreter rather than a general-purpose programming target. The interpreters running on top of PALM (the System/360 emulator and the System/3 emulator) provide higher-level control flow to their code.
 
=== GETA Priority Encoder (8-Way Hardware Dispatch) ===
 
The '''GETA''' instruction (opcode `0xyF`) is one of PALM's most distinctive hardware features. GETA performs an 8-way priority decode of the 8 bits on Bus In, mapping the position of the leftmost zero into an addend of 0, 2, 4, 6, 8, A, C, or E (always even), which is then added to the destination register.
 
When the destination register is '''R0''' (the IAR), GETA becomes an '''8-way computed dispatch in a single instruction''' — the canonical "jump table in hardware" mechanism used throughout the executable ROS to dispatch I/O interrupts and emulated S/360 opcode classes. Without GETA the same dispatch would require a longer skip-chain.
 
=== Per-Instruction Timing (SY31-0405-3 Figure 11) ===
 
The 5100 MIM Figure 11 (transcribed by Corti from the IBM Sindelfingen archive) gives the per-instruction execution time when fetching from RWS. The bracketed values are the equivalent times when executing out of executable ROS — '''ROS execution is faster than RWS''' because the storage timing differs.
 
{| class="wikitable styled-table" style="width:100%; text-align:center;"
|+'''Native PALM per-instruction execution time (from RWS; bracketed values from ROS)'''
! Instruction !! From RWS !! From ROS
|-
| MOVE, MVM1, MVM2, MVP1, MVP2 || 3.97 µs || 1.52 µs
|-
| AND, ORB, XOR, ADD, SUB, ADDS1, ADDS2, HTL, LTH, GETR, GETA || 4.63 µs || 1.72 µs
|-
| CTL || 2.65 µs || 1.13 µs
|-
| PUTB || 3.97 µs || 2.05 µs
|-
| GETB, LDHI, LDBI, STHI, STBI || 4.63 µs || 2.05 µs
|-
| LDHD, STHD || 3.97 µs || 1.52 µs
|-
| EMIT || 2.65 µs || 1.13 µs
|-
| CLRI, ADDI, SUBI, SETI || 3.97 µs || 1.52 µs
|-
| All jumps (C-group skips) || 5.30 µs || 1.92 µs
|-
| Shift / rotate (E0xC–F) || 1.72 µs || —
|}
 
ROS execution is 2–3× faster than RWS execution for the same opcodes, which is part of why so much of the executive ROS is structured as monolithic ROS-resident code rather than RWS-loaded routines.
 
=== PALM Is Self-Hosting ===
 
PALM is sufficiently capable as a programming target that '''it can host its own assembler'''. IBM's GENASM PALM (H. J. Myers, 1977) is a macro-assembler generator that runs on the 5100 itself and produces PALM machine code from PALM assembly source. The full assembler build time from source on a 5100 is reported at approximately 45 minutes. This means that within IBM, PALM was used as a self-hosting development platform for its own microcode — a notable property for a 1973-era board-level processor.
 
The modern equivalent is '''Alfred Arnold's Macro Assembler AS''' (build 1.42 Bld 231, October 2022), which adds PALM as a target architecture with synthetic pseudo-opcodes — BRA, RET, CALL, JMP, LWI — layered over the IBM Chapter 2 mnemonics, giving restorers and emulator developers a modern toolchain for PALM code.


=== Branching by Skip, Not by Jump ===
=== Branching by Skip, Not by Jump ===
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| '''Arithmetic Logic Unit (ALU)''' || 8 bits || Performs ADD, SUB, AND, OR, XOR, NOT — the ALU is 8 bits wide; 16-bit operations are done in two passes
| '''Arithmetic Logic Unit (ALU)''' || 8 bits || Performs ADD, SUB, AND, OR, XOR, NOT — the ALU is 8 bits wide; 16-bit operations are done in two passes
|-
|-
| '''Control ROS''' || 256 × 32 bits || The microcode store on the PALM module itself; the Op Reg indexes into this ROS to produce the 32-bit control word that drives the rest of the cycle
| '''Control ROS''' || Width unverified || The microcode store on the controller card; the Op Reg indexes into this ROS to produce the control word that drives the rest of the cycle. The 256 × 32-bit figure that previously appeared on this page is a Wikipedia talk-page rumour not confirmed by SY31-0405-3
|-
|-
| '''Register File''' || 16 × 16 × 4 = 64 × 16 bits || General-purpose registers — 16 per interrupt level × 4 levels
| '''Register File''' || 16 × 16 × 4 = 64 × 16 bits || General-purpose registers — 16 per interrupt level × 4 levels
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== Microcode and Emulated Instruction Sets ==
== Microcode and Emulated Instruction Sets ==


PALM is most often described in IBM literature as a '''microprogrammed processor''' — meaning the small 16-bit native instruction set is itself implemented by a 32-bit-wide microcode store on the PALM module, and that microcode can also implement '''higher-level emulated instruction sets'''.
PALM is best described as a '''microprogrammed processor''' that runs three layered instruction sets at different times:
 
# '''Native PALM ISA''' (16-bit halfword instructions, decoded by the control ROS on the controller card) — used by IBM's own diagnostics, the GENASM-assembled microcode, and the executive ROS itself.
# '''IBM System/360 subset''' — implemented by an emulator written in native PALM microcode, sitting in the executable ROS. Used only by the APL environment.
# '''IBM System/3 Model 6 subset''' — implemented by a separate emulator in PALM microcode. Used only by the BASIC environment.
 
=== The System/360 Emulator (APL only) ===
 
The APL executable ROS contains an IBM System/360 emulator written in PALM microcode. The non-executable APL ROS (cards C2 / D2 / D4 on the 5100) contains the APL interpreter '''as System/360 object code''', which the executive ROS interprets opcode-by-opcode.
 
This is confirmed by two independent reverse-engineering efforts:
 
* '''Christian Corti''' (Stuttgart Computer Museum) disassembled the executive ROS in his `aplros.asm` file: "The APL executable ROS is mainly a System/360 emulator that executes the APL interpreter in 360 code from the non-executable ROS."
* '''Brett W. Hill''' (voidstar.blog) reviewed the same disassembly and found '''only System/360 opcodes''' in the dispatch handlers — no System/370-specific instructions.
 
The earlier widely-circulated claim that PALM contained an "IBM System/370 emulator" is '''not borne out by direct examination of the executive ROS'''. The confusion arises because IBM's APL implementation on mainframes (APLSV) ran on System/370 — but the 5100's port of APLSV was compiled / re-targeted to System/360 object code for execution on PALM, not S/370 code.
 
The full System/360 opcode subset implemented by the emulator is not published; the canonical source for the actual subset is Corti's `aplros.asm` file at `ftp://ftp.informatik.uni-stuttgart.de/pub/cm/ibm/ibm5110/`. Inference from public material:
 
* '''Out of scope''': floating-point hardware (APL uses software FP routines), decimal arithmetic, privileged S/360 instructions (SVC, LPSW, storage protection).
* '''In scope''': integer and logical instructions, the addressing modes APL needs, character / packed-data operations the interpreter exercises.
 
=== The System/3 Emulator (BASIC only) ===
 
The BASIC environment is built on a separate System/3 Model 6 emulator. The BASIC interpreter is itself System/3 object code, and the executable BASIC ROS interprets that code via the System/3 emulator.
 
=== Native PALM ISA Word Size ===
 
Native PALM instructions are '''16-bit halfwords'''. An older internet rumour (preserved in the Wikipedia talk page) claims that the control ROS on the PALM card itself is "32 bits wide" internally — but this claim cannot be confirmed in any primary source the wiki has access to. The SY31-0405-3 MIM describes the control ROS unit functionally but does not state its width. '''Treat the "32-bit internal microcode" figure as unverified.''' What is verified is that the ISA exposed to the executable ROS and to GENASM-generated PALM programs is the 16-bit halfword instruction set documented in IBM "Chapter 2" and in SY31-0405-3 Appendix C.
 
== Card Complement Around PALM ==
 
The PALM controller card does not stand alone — it is one of about a dozen cards on the IBM A1 backplane in the 5100 / 5110 / 5120, all of which it talks to over the Storage Address, Storage R/W and I/O buses. From the 5100 MIM SY31-0405-3 §4 layout diagram (p. 4-19):
 
{| class="wikitable styled-table" style="width:100%;"
|+'''5100 A1 backplane card complement'''
! Slot !! Card !! Function
|-
| '''C2 / D2 / D4''' || APL ROS (non-executable) || APL interpreter as System/360 object code; accessed via I/O DA=1
|-
| '''C4''' || BASIC ROS (non-executable, 36 KB) || BASIC interpreter as System/3 object code; accessed via I/O DA=1
|-
| '''E2''' || ROS Control / common ROS || Mux logic + common operator-message text
|-
| '''F2''' || Base I/O || Bus-In / Bus-Out / strobes interface to the controller card
|-
| '''G2''' || '''Controller (PALM)''' || The 13-Dutchess processor card; '''this article's subject'''
|-
| '''H2''' || BASIC executable ROS || PALM microcode implementing the System/3 emulator + I/O + diagnostics for BASIC mode
|-
| '''H4''' || APL executable ROS || PALM microcode implementing the System/360 emulator + I/O + diagnostics for APL mode
|-
| '''J2''' || Display adapter || Generates the 5-inch CRT video, cycle-stealing from RWS for the frame buffer at $0200–$05FF
|-
| '''K2 / K4 / L2 / L4 / M2 / M4 / N2 / N4''' || R/W storage (RWS) || Up to eight 8 KB RAM cards = 64 KB max system RWS
|-
| '''A2''' || I/O cable driver || External-bus repower for peripherals (5103 printer, 5106 tape, etc.)
|}
 
The 5110 reorganises this: the controller card is in '''slot J2''' instead of G2, RWS uses two 16 KB cards instead of eight 8 KB cards, and a second executable-ROS card is on a different slot. The Stuttgart Computer Museum's '''Boards and Connectors''' page documents the 5110 A1 backplane in full, including the Y1, Z2, Z3 and Z4 cable pinouts.<ref>Corti, C., Stuttgart Computer Museum IBM 5110 pages, "Boards and connectors".</ref>


The 5100 family uses '''two emulation layers''':
A key consequence of the storage architecture: '''data fetches are always from RWS — executable ROS cannot be read as data from a running PALM program.''' `LDHD`, `LDHI`, `LDBI` and the indirect-load family all address RWS only. This is why extracting the executive ROS for reverse engineering required a hardware trick (see [[#Executive ROS Extraction|Executive ROS Extraction]] below).


* '''PALM microcode → System/370 APL bytecode → APL primitives''' (for the APL environment).
== Memory Map of the Running System ==
* '''PALM microcode → System/3 Model 6 instruction subset → BASIC primitives''' (for the BASIC environment).


The APL interpreter is a slightly modified '''APLSV''' (APL Shared Variables) — IBM's System/370 APL implementation. PALM microcode emulates enough of the System/370 instruction set that the unmodified APLSV object code can run.
The first 128 bytes of RWS are memory-mapped to the four banks of 16 registers (with the active bank window changing with the current interrupt level). The remainder of RWS is general-purpose RAM, with certain addresses reserved for I/O status bytes that the executable ROS keeps up to date.<ref>voidstar.blog, "IBM 5100 / 5110 memory map and acronyms" — cross-verified to SY31-0405 §3.</ref>


The BASIC interpreter is a port of IBM's '''System/3 Model 6 BASIC''' — PALM microcode emulates enough of the System/3 instruction set that the BASIC interpreter, which is itself emulated S/3 code, runs unchanged.
{| class="wikitable styled-table" style="width:100%;"
|+'''Selected RWS addresses (5100 / 5110)'''
! Address !! Contents
|-
| $0000–$001F || Register file, interrupt level 0 (R0L0 = IAR; R1L0 = link register)
|-
| $0020–$003F || Register file, interrupt level 1
|-
| $0040–$005F || Register file, interrupt level 2
|-
| $0055 || Printer Status Byte A (low byte of R10L2)
|-
| $0057 || Printer Status Byte B (low byte of R11L2)
|-
| $0060–$007F || Register file, interrupt level 3
|-
| $008F || Tape Status Byte
|-
| $00A8 || Last byte of RWS (5100) — varies; 5110 last byte is $00AA
|-
| $00AC || Address of the RWS / ROS switch routine
|-
| $00AE || Address of the I/O supervisor
|-
| $00E8 / $00E9 || Disk Status Byte A / B (5110 only)
|-
| $0200–$05FF || Display buffer (memory-mapped 64 × 16-character screen)
|}


'''Crucially, the System/370 emulator is APL-only — BASIC uses the System/3 emulator instead.''' This was confirmed by IBM engineers on the alt.folklore.computers thread "John Titor was right? IBM 5100" — IBM never disclosed the emulator's existence in customer-facing literature.
The I/O supervisor exposes a 14-byte IOCB (I/O Control Block) for each device; the layout is documented at the Stuttgart Computer Museum's IOCB page.<ref>Corti, C., Stuttgart Computer Museum, "IOCB layout".</ref>


This layered emulation explains why the [[IBM 5100]] became famous in the John Titor Internet hoax in 2000–2001: the central claim of the hoax — that the 5100 secretly contained an IBM System/360 emulator — is '''substantially true at the architectural level'''.
== ROS Organisation ==


=== What is in the S/370 / S/3 Subsets ===
The 5100 / 5110 ROS comes in two distinct flavours:


The exact subset of System/370 (and System/3) instructions emulated by PALM microcode '''is not documented in any publicly available source''' that this article's research could locate. IBM did not disclose the subset; the manuals describe the user-facing APL and BASIC interpreters but not the emulation layer beneath them.
* '''Executable ROS''' — directly addressable by the Storage Address Bus. Contains PALM microcode the controller fetches and executes through I-phase / E-phase cycles. The executive ROS includes the System/360 emulator (APL mode) or the System/3 emulator (BASIC mode), all of the I/O drivers, and the Diagnostic Control Program.
* '''Non-executable ROS''' — accessed only as a peripheral via device address 1 (Common + Language ROS) or device address 2 (Executable ROS on 5110; used for bank switching). Contains the APL interpreter (S/360 object code) and the BASIC interpreter (S/3 object code) plus the operator-message common ROS.


Reasonable inferences (not verified):
The non-executable ROS is read a byte at a time by:


* '''Floating-point hardware''' — out of scope (APLSV uses software floating-point routines anyway on the 5100).
# `CTL DA=1, command-byte` to load the 16-bit ROS address.
* '''Decimal arithmetic''' (S/370 packed decimal instructions) — likely out of scope.
# `PUTB DA=1, high-byte ; PUTB DA=1, low-byte` to clock the address into the ROS counter.
* '''Privileged S/370 instructions''' (SVC, LPSW, STORAGE PROTECTION ops) — out of scope.
# `GETB DA=1, Rx` reads the byte at that address and auto-increments the counter for the next read.
* '''Integer and logical instructions''' as exercised by APLSV bytecode — in scope.
* '''Memory addressing modes''' as used by APLSV — in scope.


The S/370 subset is therefore "what APLSV actually exercises", not "all of S/370".
Three control lines coordinate the access — '''−Restart''', '''−Set''', '''−Sample-and-Reset''' — driven by ROS access clocks MCC2, MCC3 and MCC4. MCC4 resets the array between transfers; (MCC2 × MCC3) gates the data out.<ref>Corti, C., Stuttgart Computer Museum, "Special I/O" page.</ref>
 
Notably, '''bit 0 of the CTL byte to DA=1 is "ROS write enable"''' — Corti speculates this almost certainly existed so IBM developers could test new ROS images on production hardware without burning new mask ROMs (the 5100 development era overlapped with 1702 / 2708 EPROM technology).
 
== Executive ROS Extraction ==
 
Because executable ROS cannot be read as data from a running PALM program (see [[#Card Complement Around PALM|Card Complement]] above), reverse-engineering the executive ROS required exploiting a hardware feature of the 5100 / 5110 boot sequence:
 
# On the very first machine cycle after power-on, the display adapter shows the 512 bytes of executive ROS at whatever address the SAB jumpers point to (default 0x0000).
# The internal '''Single-Step switch''' (accessible through the case via two screws) lets the field engineer freeze the machine on that first cycle.
# Pulling the SAB jumpers to different addresses lets you walk through all 128 × 512-byte = '''64 KB pages''' of executive ROS, photographing each frozen frame.
 
Christian Corti applied this to the '''5110''' between 2007 and 2012, photographing every page at high resolution and OCR-ing the result.
 
'''Tom Stepleton and Corti''' repeated the procedure on a '''5100''' in January 2019, using AI-guided OCR followed by manual correction. The full project notebook is at `github.com/stepleton/5100ExecutableROSDecode`; the decoded ROS images are archived at `archive.org/details/ibm_5100_ros`.
 
The non-executable ROS — APL on C2 / D2 / D4 (5100) and BASIC on C4 — is extracted in software, not by display-trickery, because it is reachable as an I/O device. A small PALM program written via the Diagnostic Control Program loops `CTL DA=1, #$04 ; PUTB-addr ; GETB-data` to dump non-executable ROS into RWS, then a DCP-driven RWS-to-disk dump and a KERMIT transfer to a modern host completes the extraction. The full DCP listing is documented by Corti at the Stuttgart Computer Museum's "Extracting the non-executable ROS" page.


== Process Check and Diagnostic Features ==
== Process Check and Diagnostic Features ==
Line 456: Line 666:


A '''Diagnostic ROS''' mode is entered via a keyboard sequence at power-on; in this mode the operator can read and write RAM, video memory, PALM registers, interrupt vectors and the clock counter in hex — effectively assembly-language access to PALM without an operating system.
A '''Diagnostic ROS''' mode is entered via a keyboard sequence at power-on; in this mode the operator can read and write RAM, video memory, PALM registers, interrupt vectors and the clock counter in hex — effectively assembly-language access to PALM without an operating system.
== Significance ==
* '''Predates the Intel 8086 (June 1978) by ~3 years and the Intel 8080 (April 1974) by months''' (SCAMP, with PALM, was running in June 1973).
* '''Not a single-chip CPU.''' IBM in the 1970s used "microprocessor" to mean "processor that executes microcode to implement a higher-level instruction set" — not the modern meaning of "single integrated circuit". The Roberson 1976 IEEE paper title — "A Microprocessor-based portable computer: The IBM 5100" — uses "microprocessor" in this sense.
* '''The only IBM CPU of its generation.''' The IBM 801 RISC project at IBM Research/Yorktown Heights began in 1975 and is a completely independent programme; there is no architectural lineage between PALM and 801. The 5100 / 5110 / 5120 are the only commercial IBM machines built on PALM.
* '''First IBM emulation-by-microcode implementation in a small machine.''' The pattern of "small computer that emulates a larger architecture in microcode to run unmodified mainframe binaries" was later reused by IBM in the '''XT/370''' (1983), where an IBM PC XT was fitted with a System/370 emulator card.
* '''Cultural footprint.''' The 5100 — and through it, PALM — became famous in the John Titor Internet hoax of 2000–2001 for being claimed to secretly emulate a System/360. The claim is substantively true.


== Known Gaps in Documentation ==
== Known Gaps in Documentation ==


This article documents PALM at the level supported by publicly available sources. The following details are '''documented in IBM's CE manuals but not in any widely-mirrored secondary source''', and are listed as gaps for future research:
This article documents PALM at the level supported by publicly available primary and reverse-engineering sources. The following details are documented in IBM's CE manuals but '''not'''  transcribed into any widely-mirrored secondary source, and remain open gaps:


# '''The one-to-one mapping of the 13 Dutchess gate arrays onto the PALM function blocks.''' The IBM part numbers for all 13 gate arrays are now identified on this page (see [[#Identified ICs on the PALM Board|"Identified ICs on the PALM Board"]] above), but '''which function each part implements''' (ALU, register file, microcode sequencer, bus interface, etc.) is documented only in IBM 5100 MIM SY31-0405 (PALM appendix) and IBM 5120 CSLM SY34-0193, and has not been transcribed into any community-accessible secondary source.
# '''Function-block to gate-array mapping.''' The 13 Dutchess gate array part numbers are identified on this page (see [[#Identified ICs on the PALM Board|Identified ICs on the PALM Board]] above), but '''which function each chip implements''' (ALU, register file, microcode sequencer, bus interface, etc.) is documented only in IBM 5100 MIM SY31-0405 §4 "Theory" / "5100 Controller Description" and IBM 5120 CSLM SY34-0193, '''neither of which uses the term "PALM" or names individual gate-array part numbers'''. SY31-0405 §4 documents the function blocks as named signals (RDR, SAR, Op Reg, SDR, ALU Reg, ALU, Control ROS Unit) but stops short of saying "function block X is implemented by chip part-number Y". Closing this gap requires direct gate-level tracing of the controller card against the CSLM logic flowcharts.
# '''The function (not just the part number) of the 3 TTL DIPs and 1 round metal-can device on the PALM board.''' The part numbers '''210086-C''' / '''M-210086-C''' for the small DIPs and the visual identification of the round metal can as a crystal-oscillator can are now recorded here. The exact role of the 210086-C devices in the PALM design is documented in the CSLM but not in any secondary source.
# '''Function of the small 210086-C / M-210086-C DIPs.''' The part numbers are now recorded from the J2 card photograph but the function within the controller is not documented in any source the wiki has access to. The 7825 / 7828 date codes (weeks 25 and 28 of 1978) confirm the J2 card was built mid-1978, consistent with a 1978 5110.
# '''The exact System/370 instruction subset emulated by PALM microcode.''' IBM did not publish this; the manuals deliberately omit the emulation layer.
# '''Exact System/360 instruction subset emulated.''' The canonical source is Corti's `aplros.asm` (the disassembled APL executable ROS) at `ftp://ftp.informatik.uni-stuttgart.de/pub/cm/ibm/ibm5110/`. No source enumerates the subset as a discrete instruction list. The previous version of this page identified the emulator as "System/370" — that claim is incorrect; direct disassembly shows only S/360 opcodes.
# '''Die-shot or photomicrograph of a Dutchess masterslice.''' No publicly available example.
# '''Exact System/3 Model 6 instruction subset emulated by the BASIC ROS.''' Same status — emulator exists, opcode list not published.
# '''Whether PALM was used in any other IBM product as an embedded controller.''' Wikipedia notes "It is likely PALM was also used in other IBM products as an embedded controller" — no cited example. Speculation on Hacker News about the IBM 3274 cluster controller is unverified.
# '''Die-shot or photomicrograph of a Dutchess masterslice.''' None located publicly.
# '''Exact PALM board dimensions, weight and per-card power draw.''' Not separately documented from the rest of the A1 backplane card family.
# '''Use of PALM in other IBM products as an embedded controller.''' Wikipedia speculates ("It is likely PALM was also used in other IBM products as an embedded controller") but no source has identified a specific product. Speculation on Hacker News thread 14483823 about the '''IBM 3274 cluster controller''' is anecdotal (vt240 noted "square metal cans, many of them socketed" matching the visual signature of IBM masterslice modules of the period) but '''unverified''' against IBM documentation.
# '''Exact PALM board dimensions, weight and per-card power draw.''' Y1 power-feed cable on the 5110 A1 backplane supplies +5 V, +8.5 V, +12 V, −5 V, −12 V to the controller card among others — exact controller-only current draw not separately documented.
# '''Roberson 1976 ''Proceedings of the IEEE'' paper full text.''' Available only through paywalled IEEE Xplore or behind environment blocklists. Cited extensively for the 1.75 µs average microinstruction figure, but the wiki cannot independently verify against the original.
# '''Internal width of the control ROS / microcode store on the controller card.''' Wikipedia-talk-page claim of "256 × 32 bits" cannot be confirmed against SY31-0405-3, which describes the control ROS unit functionally without giving width. Treat as unverified.


== Related Pages ==
== Related Pages ==
Retrieved from "https://wiki.retrotechcollection.com/IBM_PALM_processor"