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PDP-10

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PDP-10
KA10 PDP-10 systems at Bolt Beranek and Newman, around 1970 (public domain)
Specifications
ManufacturerDigital Equipment Corporation
Type36-bit mainframe
ReleasedMade from 1966; first deliveries December 1967[1]
Discontinued1983 (cancellation announced)[1]
CPUKA10, KI10, KL10, KS10[1]
MemoryCore memory, 256K words maximum on the KA10; 4096K words on the KI10[1][2]
Storage—
Display—
Sound—
PowerKA10 processor: 115/200 V three-phase, 4300 W[3]
OS / FirmwareTOPS-10 (Monitor), TOPS-20, TENEX, ITS, WAITS[1]

The PDP-10 is Digital Equipment Corporation's family of 36-bit time-sharing computers, made from 1966 and delivered from December 1967 until DEC announced the end of the line in 1983. Systems from the 1970s were sold under the name DECsystem-10, and the KL10 and KS10 also formed the DECSYSTEM-20 range.[1] The architecture is almost that of DEC's earlier PDP-6: 36-bit words, 18-bit addresses giving 256K words, sixteen general registers, and byte instructions that work on fields of any width from 1 to 36 bits.[1]

Four processors were built, from discrete-transistor FLIP CHIP logic to bit-slice microprocessors, and each needs different maintenance. The PDP-10 guides give most detail for the KA10, the original processor, and the KS10, the smallest; the KL10-based DECsystem-10 systems have their own pages starting at DECsystem-10. See PDP-10 General Maintenance, PDP-10 Power System Service and PDP-10 Troubleshooting Guide.

Processors

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PDP-10 processors
Processor Introduced Technology Notes
KA10 1968 Discrete transistors on FLIP CHIP modules, wire-wrapped backplanes 1 µs cycle, 2.1 µs add; base-and-bounds protection, no paging; 256K words
KI10 1973 TTL small-scale ICs Paging; 4096K words physical; DECsystem-1060, 1070, 1077
KL10 1975 ECL DECsystem-1080 to 1099 and DECSYSTEM-20 models; see DECsystem-10
KS10 1978 TTL and Am2901 bit-slices, Intel 8080A console processor DECSYSTEM-2020; Unibus peripherals

[1][2] The KI10 runs the same monitor, software and most peripherals as the KA10, so a KA10 system could be upgraded without changing user programs.[2]

KA10

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The KA10 processor fills three 31-inch cabinets. The right-hand bay holds the paper-tape reader and punch, the operator's console and, optionally, two TU55 DECtape drives; to the left of the reader and punch is the margin check and maintenance panel. Behind the hinged front doors are up to sixteen module panels (A to T, without G, I, O and Q), each holding 44 FLIP CHIP modules in the 31-inch cabinets. The power supplies are on a hinged frame inside the rear door, and fans or blowers cool the cabinets.[4] The KA10 processes 36-bit words and addresses up to 262,144 words of core memory. DEC sold five basic systems, the PDP-10/10 to 10/50.[4]

DEC's site guide gives the processor's installation data:[3]

KA10 arithmetic processor installation data (PDP-10 Site Preparation Guide, 1970)
Item Value
Mains 115/200 V ±10%, 60 Hz ±2%, three-phase, 4-wire plus ground (230/400 V 50 Hz for 50 Hz systems)
Current at 115 V 11 A phase 1 (16 A with the punch on), 11 A phase 2, 14 A phase 3; surge 25 A per phase
Power and heat 4300 W, 14,720 Btu/h
Size 69 × 96.5 × 49.5 in (1.75 × 2.45 × 1.26 m)
Weight 1930 lb (875 kg)
Operating environment 15–35 °C, 20–80% relative humidity

[3]

KS10

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The KS10, sold as the DECSYSTEM-2020, uses AMD 2901 bit-slice parts and an Intel 8080A as console and control processor. The 8080 loads the microcode from disk or tape, starts the main processor, and then runs the console and remote diagnostic ports. Peripherals are on the PDP-11 Unibus.[1] The machine boots itself 30 seconds after power-up.[5] Its logic is powered by H7130 supplies, and Unibus options sit in a BA11-K box with its own supply and adjustments.[6]

Operating systems

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DEC's original operating system, called Monitor, became TOPS-10. BBN's TENEX was ported by DEC to the KL10 and became TOPS-20. MIT ran its own ITS, and Stanford's WAITS grew out of early TOPS-10.[1]

Documentation

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See PDP-10 Documentation.

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  • KA10 FLIP CHIP module (Jnc, CC BY-SA 2.5)
    KA10 FLIP CHIP module (Jnc, CC BY-SA 2.5)
  • DECSYSTEM-2020 (KS10) (Jason Scott, CC BY 2.0)
    DECSYSTEM-2020 (KS10) (Jason Scott, CC BY 2.0)
  • DECsystem-10 with KI10 processor (Gah4, CC BY-SA 4.0)
    DECsystem-10 with KI10 processor (Gah4, CC BY-SA 4.0)
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References

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  1. ↑ 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 "PDP-10", Wikipedia, en.wikipedia.org/wiki/PDP-10. Dates, architecture, processors, KS10 design, operating systems.
  2. ↑ 2.0 2.1 2.2 Digital Equipment Corporation, DECsystem-10 Technical Summary, 1971, pp. 16 and 37 (File:DECsystem-10 Technical Summary (1971).pdf).
  3. ↑ 3.0 3.1 3.2 Digital Equipment Corporation, PDP-10 Site Preparation Guide, DEC-10-HAAB-D, May 1970, KA10 arithmetic processor data sheet and electrical requirements (File:PDP-10 Site Preparation Guide (DEC-10-HAAB-D).pdf).
  4. ↑ 4.0 4.1 Digital Equipment Corporation, PDP-10 KA10 Central Processor Maintenance Manual, Volume I, DEC-10-HMAA-D, December 1968, chapter 1, sections 1.1.1 and 1.1.2 (File:PDP-10 KA10 Central Processor Maintenance Manual Volume I (DEC-10-HMAA-D).pdf).
  5. ↑ Digital Equipment Corporation, KS10 Maintenance Guide, Volume I, EK-OKS10-MG-001, June 1979, system software section, standard boot procedure (File:KS10 Maintenance Guide Volume 1 (EK-OKS10-MG-001).pdf).
  6. ↑ DEC, EK-OKS10-MG-001, checks/adjustments section: KS10 backplane power adjustment, H7130 power supply, BA11-K backplane power adjustments.
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