Super Nintendo Entertainment System: Difference between revisions
Cite from Nintendo's Playtronic manual and Japanese service manual: remove 'Project Reality' (that is the N64's codename, not the SNES's); correct the supply to 10 V DC 850 mA centre negative with no 12 V or 3.3 V rail; correct the sound subsystem description; add the GPM revision, the 62-pin connector, F1, U12 and the C67 discharge warning; remove unsourced dimensions, weight and price; replace red links with real targets |
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| name = Super Nintendo Entertainment System | | name = Super Nintendo Entertainment System | ||
| image = [[File:SNES-Mod1-Console-Set.jpg|250px]] | | image = [[File:SNES-Mod1-Console-Set.jpg|250px]] | ||
| caption = North American Super Nintendo Entertainment System | | caption = North American Super Nintendo Entertainment System | ||
| manufacturer = Nintendo | | manufacturer = Nintendo | ||
| type = Home video game console | | type = Home video game console | ||
| release date = JP: 21 November 1990<br>NA: 23 August 1991<br>EU: 11 April 1992 | | release date = JP: 21 November 1990<br>NA: 23 August 1991<br>EU: 11 April 1992 | ||
| discontinued = JP: 2003<br>NA: 1999<br>EU: 1998 | | discontinued = JP: 2003<br>NA: 1999<br>EU: 1998 | ||
| cpu = Ricoh 5A22, 65C816 core, 3.58 / 2.68 / 1.79 MHz selected per access | |||
| cpu = Ricoh 5A22 | | memory = 128 KB work RAM, 64 KB VRAM, 64 KB audio RAM | ||
| memory = 128 KB RAM, 64 KB VRAM | | storage = ROM cartridge, 62-pin connector | ||
| storage = ROM cartridge | | display = 256×224 to 512×448; 32,768-colour palette | ||
| display = 256×224 to 512×448 | | graphics = PPU1 and PPU2 (S-PPU1 / S-PPU2), Mode 7 rotation and scaling | ||
| sound = | | sound = S-SMP (SPC700 core) with S-DSP, 8 ADPCM channels, and a µPD6376 DAC | ||
| | | power = SNS-002 / HVC-002, 10 V DC 850 mA '''centre negative''' (NTSC and Japan); 9 V '''AC''' (PAL) | ||
| os = None | | os = None | ||
| predecessor = [[Nintendo Entertainment System]] | | predecessor = [[Nintendo Entertainment System]] | ||
| successor = [[Nintendo 64]] | | successor = [[Nintendo 64]] | ||
| model = SHVC-001 (Super Famicom), SNS-001 (SNES), SNS-101 (SNES Jr / SNES mini) | |||
| model = | |||
| logo = [[File:Super Nintendo Entertainment System logo.svg|250px]] | | logo = [[File:Super Nintendo Entertainment System logo.svg|250px]] | ||
}} | }} | ||
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The '''Super Nintendo Entertainment System''' ('''SNES'''), | The '''Super Nintendo Entertainment System''' ('''SNES'''), sold in Japan as the '''Super Famicom''' (スーパーファミコン), is a 16-bit home video game console developed and manufactured by Nintendo. It launched in Japan in November 1990, in North America in August 1991 and in Europe in April 1992, and competed principally with the [[Sega Mega Drive / Genesis (Model 1)|Sega Mega Drive / Genesis]]. | ||
'''Unusually for a Nintendo console of this era, a genuine Nintendo service manual for it survives''': the Playtronic ''Manual Técnico do Super NES'', Rev. 01/94, hosted here as [[Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94)]]. Most of the hardware figures on this page come from it and from Nintendo's Japanese Famicom / Super Famicom / Game Boy service manual.<ref name="playtronic">Nintendo / Playtronic, ''Manual Técnico do Super NES'', Rev. 01/94, hosted at [[Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94)]]. Console theory of operation (pp. 2-1 to 2-2): the AC adapter supplies 10 V DC unregulated; the on-board supply section comprises a noise filter, reverse-current protection, the power switch, a spike suppressor, a ripple filter and the regulator, and produces a regulated Vcc of 5 V and an unregulated Vs of 7 V used by the audio amplifier; the controller input section uses diode and capacitor arrays for surge protection and pull-up resistors, and the CPU samples the controllers about every 17 ms; the system timing section feeds a 21 MHz master clock to the CPU, PPU1, PPU2 and connector P1, and the CPU divides it by 6, 8 and 12 to give 3.58, 2.68 and 1.79 MHz, with DMA always at 2.68 MHz; the RESET section uses a 4 MHz oscillator, a 74HCU04 hex inverter, the CIC and the reset switch, and applies CIC reset to PPU2 first, then PPU1, then the CPU. Parts list: F1 a 1.5 A SSTR axial fuse, U12 a 7805, X1 a 21.453666 MHz (PAL-M) crystal, X2 a 4 MHz ceramic oscillator, and a 24.57 MHz ceramic oscillator. Adjustment and fault-finding: TC1 set to 21.453666 MHz; the 4 MHz CIC clock acceptable between 3.8 and 4.2 MHz. Disassembly: switch the console on with the AC adapter disconnected to discharge C67 before opening it. GPM section (pp. 3-1 ff.): the ground-plane mainboard removed the lower RF shield, shortened the PCB, deleted C67 and the 4 MHz oscillator, built the sound module circuit onto the mainboard, made TC1 a through-hole part, and removed the cartridge lock bar from the upper housing in favour of a warning label. IC handling notes (p. 8-2): do not measure ICs with a multimeter or signal tracer.</ref><ref name="famsm">Nintendo, ''ファミコン・スーパーファミコン・ゲームボーイ サービスマニュアル'' (Famicom / Super Famicom / Game Boy Service Manual), issued 7 August 1992, hosted at [[Nintendo Famicom Service Manual]]. HVC section, pp. 2–10: AC adapter rated DC 10 V with a normal no-load output of DC 13.5 ± 1.5 V; HVC power-circuit block diagram showing a 7805 with 13–14 V in and 5 V out, drawn in both the standard and the VCCI variant; RF switch terminal carrying DC 5 V in game mode; the three solder points that need reinforcing around the DC jack; "before you decide it is a fault" table, p. 3; controller fault symptoms and the plug-in controller connectors, p. 4; exploded parts diagrams, pp. 7–9; Famicom repair price list, p. 10 (60-pin card connector, 15-pin D-sub jack, crystal, RF modulator unit, DC jack, 7805 three-terminal regulator, fuse listed for VCCI boards only, electret microphone, CMOS 4021 and 4069 in the controllers). SHVC section, pp. 11–15: power-switch harness polarity; SHVC power circuit, 7805 with 13–14 V in and 5 V out; Super Famicom repair price list (1.5 A SSTR axial fuse, 7805, 62-pin card connector in upper and lower halves, sound module).</ref> | |||
For servicing, see [[Super Famicom Maintenance Guide]], [[Super Nintendo Troubleshooting Guide]] and [[Super Famicom Capacitor Replacement Guide]] — the boards are the same family and the guides cover Super Famicom, SNES and SNES Jr together. | |||
== | == Architecture == | ||
The CPU is the '''Ricoh 5A22''', a 65C816 core with the memory mapper, DMA controller and joypad interface on the same die. Nintendo's description of the timing section: a '''21 MHz''' master clock is distributed to the CPU, to '''PPU1''' and '''PPU2''' and to connector P1; the CPU divides it by '''6, 8 and 12''' to give '''3.58, 2.68 and 1.79 MHz'''. The core runs at 3.58 MHz, address-mapped transfers run at 2.68 MHz, and the clock switches automatically according to the access time of the device being addressed. '''DMA always runs at 2.68 MHz''', whatever the address.<ref name="playtronic" /> | |||
The exact master frequency depends on the video standard: '''21.47727 MHz''' NTSC, '''21.281370 MHz''' PAL, and '''21.453666 MHz''' on the Brazilian PAL-M machines the Playtronic manual was written for.<ref name="playtronic" /> | |||
The | |||
The reset circuit is a '''4 MHz oscillator''', a '''74HCU04''' hex inverter, the CIC lockout and the reset switch. The CIC's reset reaches '''PPU2 first''' — deliberately, to introduce a delay — then PPU1, then the CPU, so that both picture processors are running before the CPU is released.<ref name="playtronic" /> | |||
The | |||
== | == Memory == | ||
=== | 128 KB of work RAM, 64 KB of video RAM and 64 KB of audio RAM private to the sound subsystem. Cartridges carry the program and character ROM and frequently additional hardware — the Super FX, SA-1, DSP-1 and others — along with battery-backed SRAM for saves. '''The save battery is in the cartridge, not in the console''': there is no battery of any kind on an SNES mainboard. | ||
== Graphics == | |||
Two picture processors, PPU1 and PPU2, working as a pair. Resolutions run from 256×224 to 512×448, from a 32,768-colour palette, with multiple background layers, hardware sprites, transparency and mosaic effects, and the rotating and scaling '''Mode 7'''. | |||
A PPU that has failed only partially is a recognised diagnostic pattern: the machine plays most games correctly but corrupts Mode 7 effects specifically, so a Mode 7 title belongs in any test set. | |||
== Sound == | |||
A self-contained subsystem: the '''S-SMP''', containing an SPC700 core and its own RAM interface, the '''S-DSP''' providing eight ADPCM channels with echo and pitch modulation, 64 KB of audio RAM and a µPD6376 DAC. On SHVC-CPU-01 boards this lives on a separate '''SHVC-SOUND''' daughtercard held by two screws; Nintendo supplies it as a service part in its own right.<ref name="famsm" /> | |||
'''The audio amplifier runs from the unregulated supply rail, not the 5 V logic rail.'''<ref name="playtronic" /><ref name="fullsnes">Martin Korth, ''fullsnes'' — SNES hardware specifications — https://problemkaputt.de/fullsnes.htm , section "SNES Power Supply". NTSC and Japanese consoles take 10 V DC at 850 mA through a series diode, so the internal unregulated rail sits near 9 V; PAL consoles take 9 V AC and rectify it on board. A 7805 produces the only logic rail, +5 V, and the CPU, PPU and APU run solely from it; the unregulated rail feeds only the audio amplifier, and the console runs without it but silently. Also the source for the anti-eject lever fitted to the power switch of earlier consoles.</ref> A console whose unregulated rail has failed plays silently but otherwise normally — a useful discriminator when chasing a no-sound fault. | |||
== Input, output and expansion == | |||
Two controller ports on a removable "front unit" board, connected to the mainboard by a flat flexible cable through a ferrite core. '''The FFC goes in one way round''' — the unprinted face is the contact face — and fitting it reversed gives dead controller ports on an otherwise healthy console.<ref name="famsm" /> The CPU samples the controllers about every 17 ms by default, and the controller input section uses diode and capacitor arrays for surge protection with pull-up resistors to hold the logic levels.<ref name="playtronic" /> | |||
The cartridge interface is a '''62-pin''' connector, which Nintendo supplies as two service parts, an upper and a lower half.<ref name="famsm" /> Video and audio leave through the AV Multi Out, which carries composite, S-Video and RGB. There is an expansion port on the underside, unused in retail machines. | |||
Earlier consoles carry an '''anti-eject lever''' on the power switch that rides in a notch in the cartridge; on cartridges with a diagonally cut notch, pulling the cartridge switches the console off.<ref name="fullsnes" /> Nintendo removed the lock bar on the later GPM machines and substituted a warning label.<ref name="playtronic" /> | |||
== Power == | |||
{| class="wikitable styled-table" style="width:95%;" | |||
|+'''Supply and rails''' | |||
! !! Figure !! Note | |||
|- | |||
| Adapter, NTSC and Japan || '''10 V DC, 850 mA, centre negative''' || Centre pin '''0 V''', outer sleeve positive<ref name="fullsnes" /> | |||
|- | |||
| Adapter, PAL || '''9 V AC''' || Rectified on the board. Not interchangeable with the DC type | |||
|- | |||
| Adapter, no load || 12.0–15.0 V DC || Nintendo specifies 13.5 ± 1.5 V as '''normal''' for the HVC-002<ref name="famsm" /> | |||
|- | |||
| '''F1''' || 1.5 A, SSTR axial || Both Nintendo parts lists carry it<ref name="playtronic" /><ref name="famsm" /> | |||
|- | |||
| Regulator || 7805 at '''U12''' (U9 on 1CHIP and SNN boards) || 13–14 V in, 5 V out<ref name="playtronic" /><ref name="famsm" /> | |||
|- | |||
| '''Vcc''' || 5.0 V || The '''only''' regulated rail. CPU, PPU1, PPU2 and APU all run from it<ref name="playtronic" /> | |||
|- | |||
| '''Vs''' || unregulated, ~7 V by Nintendo's figure || Feeds '''only''' the audio amplifier<ref name="playtronic" /> | |||
|} | |||
'''There is no +12 V rail and no 3.3 V rail in this machine.''' The on-board supply section is a noise filter, reverse-current protection, the power switch, a spike suppressor, a ripple filter and the regulator — nothing else.<ref name="playtronic" /> | |||
== Board revisions == | |||
Read the revision off the PCB silkscreen, not the case label. The families are '''SHVC-CPU''' (Japan), '''SNS-CPU''' (North America), '''SNSP-CPU''' (PAL) and '''SNN-CPU''' (SNES Jr / SNES mini), each with its own designator scheme — the C57–C67 numbering of the early boards does not survive into the later single-chip revisions. Per-revision capacitor lists are on [[Super Famicom Capacitor Replacement Guide]]. | |||
'''The GPM boards''' are a distinct redesign Nintendo documents directly. GPM is a ground-plane construction that put a base layer between the track layout and the solder mask, which let Nintendo delete the lower RF shield. Along with it: a shorter PCB, '''C67 and the 4 MHz oscillator removed''', the sound module circuit built onto the mainboard instead of a daughtercard, TC1 changed to a through-hole part, and the cartridge lock bar removed from the upper housing. The lower housing and the upper RF shield were changed to suit.<ref name="playtronic" /> | |||
'''"1CHIP" is not a GPM board and GPM is not a 1CHIP board.''' The 1CHIP revisions (SNS-CPU-1CHIP-01/-02/-03 and their PAL equivalents) merged CPU and PPUs into a single package later in the machine's life and are prized for their video output; the GPM change is a PCB manufacturing change from much earlier. | |||
== Servicing == | |||
{| class="wikitable styled-table" style="width:85%;" | |||
|+'''Where to look''' | |||
! Topic !! Page | |||
|- | |||
| Preventive care, Nintendo's diagnostic table, connectors || [[Super Famicom Maintenance Guide]] | |||
|- | |||
| Fault-finding, test points, clocks and reset || [[Super Nintendo Troubleshooting Guide]] | |||
|- | |||
| Capacitors, by board revision || [[Super Famicom Capacitor Replacement Guide]] | |||
|} | |||
'''Before opening any Super Nintendo, switch it on with the adapter disconnected to discharge C67.''' This is Nintendo's own first disassembly instruction, and the reason it gives is that C67 discharges during maintenance and damages components.<ref name="playtronic" /> | |||
Documents hosted here: [[Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94)]], [[Nintendo Famicom Service Manual]] (which also covers the SHVC) and [[SNES Schematic]]. | |||
=== Motherboard and schematic === | |||
<gallery mode="packed"> | <gallery mode="packed"> | ||
File:SNES-CPU-RGB-01 motherboard.jpg| | File:SNES-CPU-RGB-01 motherboard.jpg|SNS-CPU-RGB-01 mainboard | ||
File:Nintendo Super NES PPU chips.jpg| | File:Nintendo Super NES PPU chips.jpg|PPU1 and PPU2 | ||
File: | File:Snes schematic-1.png|SNES schematic | ||
</gallery> | </gallery> | ||
== | == Gallery == | ||
<gallery mode="packed"> | <gallery mode="packed"> | ||
File:SNES-Mod1-Console-Set.jpg|North American SNES | File:SNES-Mod1-Console-Set.jpg|North American SNES | ||
File:Nintendo-Super-Famicom-Set-FL.jpg|Super Famicom (Japan) | File:Nintendo-Super-Famicom-Set-FL.jpg|Super Famicom (Japan) | ||
File:Wikipedia SNES PAL.jpg|PAL SNES (Europe) | File:Wikipedia SNES PAL.jpg|PAL SNES (Europe) | ||
File:SNES-Controller.jpg|SNES | File:SNES-Controller.jpg|SNES controller | ||
</gallery> | </gallery> | ||
== | == Related pages == | ||
* [[Nintendo Entertainment System]] | * [[Nintendo Entertainment System]] | ||
* [[Nintendo 64]] | * [[Nintendo 64]] | ||
* [[Sega Mega Drive / Genesis (Model 1)]] | |||
* [[List of Nintendo Hardware]] | |||
== References == | |||
<references /> | |||
[[Category: Nintendo]] | [[Category:Nintendo]] | ||
Latest revision as of 18:43, 23 September 2026
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 | |
| North American Super Nintendo Entertainment System | |
| Specifications | |
|---|---|
| Manufacturer | Nintendo |
| Type | Home video game console |
| Released | JP: 21 November 1990 NA: 23 August 1991 EU: 11 April 1992 |
| Discontinued | JP: 2003 NA: 1999 EU: 1998 |
| CPU | Ricoh 5A22, 65C816 core, 3.58 / 2.68 / 1.79 MHz selected per access |
| Memory | 128 KB work RAM, 64 KB VRAM, 64 KB audio RAM |
| Storage | ROM cartridge, 62-pin connector |
| Display | 256×224 to 512×448; 32,768-colour palette |
| Sound | S-SMP (SPC700 core) with S-DSP, 8 ADPCM channels, and a µPD6376 DAC |
| Graphics | PPU1 and PPU2 (S-PPU1 / S-PPU2), Mode 7 rotation and scaling |
| Power | SNS-002 / HVC-002, 10 V DC 850 mA centre negative (NTSC and Japan); 9 V AC (PAL) |
| OS / Firmware | None |
| Predecessor | Nintendo Entertainment System |
| Successor | Nintendo 64 |
| Model no. | SHVC-001 (Super Famicom), SNS-001 (SNES), SNS-101 (SNES Jr / SNES mini) |
The Super Nintendo Entertainment System (SNES), sold in Japan as the Super Famicom (スーパーファミコン), is a 16-bit home video game console developed and manufactured by Nintendo. It launched in Japan in November 1990, in North America in August 1991 and in Europe in April 1992, and competed principally with the Sega Mega Drive / Genesis.
Unusually for a Nintendo console of this era, a genuine Nintendo service manual for it survives: the Playtronic Manual Técnico do Super NES, Rev. 01/94, hosted here as Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94). Most of the hardware figures on this page come from it and from Nintendo's Japanese Famicom / Super Famicom / Game Boy service manual.[1][2]
For servicing, see Super Famicom Maintenance Guide, Super Nintendo Troubleshooting Guide and Super Famicom Capacitor Replacement Guide — the boards are the same family and the guides cover Super Famicom, SNES and SNES Jr together.
Architecture
[edit | edit source]The CPU is the Ricoh 5A22, a 65C816 core with the memory mapper, DMA controller and joypad interface on the same die. Nintendo's description of the timing section: a 21 MHz master clock is distributed to the CPU, to PPU1 and PPU2 and to connector P1; the CPU divides it by 6, 8 and 12 to give 3.58, 2.68 and 1.79 MHz. The core runs at 3.58 MHz, address-mapped transfers run at 2.68 MHz, and the clock switches automatically according to the access time of the device being addressed. DMA always runs at 2.68 MHz, whatever the address.[1]
The exact master frequency depends on the video standard: 21.47727 MHz NTSC, 21.281370 MHz PAL, and 21.453666 MHz on the Brazilian PAL-M machines the Playtronic manual was written for.[1]
The reset circuit is a 4 MHz oscillator, a 74HCU04 hex inverter, the CIC lockout and the reset switch. The CIC's reset reaches PPU2 first — deliberately, to introduce a delay — then PPU1, then the CPU, so that both picture processors are running before the CPU is released.[1]
Memory
[edit | edit source]128 KB of work RAM, 64 KB of video RAM and 64 KB of audio RAM private to the sound subsystem. Cartridges carry the program and character ROM and frequently additional hardware — the Super FX, SA-1, DSP-1 and others — along with battery-backed SRAM for saves. The save battery is in the cartridge, not in the console: there is no battery of any kind on an SNES mainboard.
Graphics
[edit | edit source]Two picture processors, PPU1 and PPU2, working as a pair. Resolutions run from 256×224 to 512×448, from a 32,768-colour palette, with multiple background layers, hardware sprites, transparency and mosaic effects, and the rotating and scaling Mode 7.
A PPU that has failed only partially is a recognised diagnostic pattern: the machine plays most games correctly but corrupts Mode 7 effects specifically, so a Mode 7 title belongs in any test set.
Sound
[edit | edit source]A self-contained subsystem: the S-SMP, containing an SPC700 core and its own RAM interface, the S-DSP providing eight ADPCM channels with echo and pitch modulation, 64 KB of audio RAM and a µPD6376 DAC. On SHVC-CPU-01 boards this lives on a separate SHVC-SOUND daughtercard held by two screws; Nintendo supplies it as a service part in its own right.[2]
The audio amplifier runs from the unregulated supply rail, not the 5 V logic rail.[1][3] A console whose unregulated rail has failed plays silently but otherwise normally — a useful discriminator when chasing a no-sound fault.
Input, output and expansion
[edit | edit source]Two controller ports on a removable "front unit" board, connected to the mainboard by a flat flexible cable through a ferrite core. The FFC goes in one way round — the unprinted face is the contact face — and fitting it reversed gives dead controller ports on an otherwise healthy console.[2] The CPU samples the controllers about every 17 ms by default, and the controller input section uses diode and capacitor arrays for surge protection with pull-up resistors to hold the logic levels.[1]
The cartridge interface is a 62-pin connector, which Nintendo supplies as two service parts, an upper and a lower half.[2] Video and audio leave through the AV Multi Out, which carries composite, S-Video and RGB. There is an expansion port on the underside, unused in retail machines.
Earlier consoles carry an anti-eject lever on the power switch that rides in a notch in the cartridge; on cartridges with a diagonally cut notch, pulling the cartridge switches the console off.[3] Nintendo removed the lock bar on the later GPM machines and substituted a warning label.[1]
Power
[edit | edit source]| Figure | Note | |
|---|---|---|
| Adapter, NTSC and Japan | 10 V DC, 850 mA, centre negative | Centre pin 0 V, outer sleeve positive[3] |
| Adapter, PAL | 9 V AC | Rectified on the board. Not interchangeable with the DC type |
| Adapter, no load | 12.0–15.0 V DC | Nintendo specifies 13.5 ± 1.5 V as normal for the HVC-002[2] |
| F1 | 1.5 A, SSTR axial | Both Nintendo parts lists carry it[1][2] |
| Regulator | 7805 at U12 (U9 on 1CHIP and SNN boards) | 13–14 V in, 5 V out[1][2] |
| Vcc | 5.0 V | The only regulated rail. CPU, PPU1, PPU2 and APU all run from it[1] |
| Vs | unregulated, ~7 V by Nintendo's figure | Feeds only the audio amplifier[1] |
There is no +12 V rail and no 3.3 V rail in this machine. The on-board supply section is a noise filter, reverse-current protection, the power switch, a spike suppressor, a ripple filter and the regulator — nothing else.[1]
Board revisions
[edit | edit source]Read the revision off the PCB silkscreen, not the case label. The families are SHVC-CPU (Japan), SNS-CPU (North America), SNSP-CPU (PAL) and SNN-CPU (SNES Jr / SNES mini), each with its own designator scheme — the C57–C67 numbering of the early boards does not survive into the later single-chip revisions. Per-revision capacitor lists are on Super Famicom Capacitor Replacement Guide.
The GPM boards are a distinct redesign Nintendo documents directly. GPM is a ground-plane construction that put a base layer between the track layout and the solder mask, which let Nintendo delete the lower RF shield. Along with it: a shorter PCB, C67 and the 4 MHz oscillator removed, the sound module circuit built onto the mainboard instead of a daughtercard, TC1 changed to a through-hole part, and the cartridge lock bar removed from the upper housing. The lower housing and the upper RF shield were changed to suit.[1]
"1CHIP" is not a GPM board and GPM is not a 1CHIP board. The 1CHIP revisions (SNS-CPU-1CHIP-01/-02/-03 and their PAL equivalents) merged CPU and PPUs into a single package later in the machine's life and are prized for their video output; the GPM change is a PCB manufacturing change from much earlier.
Servicing
[edit | edit source]| Topic | Page |
|---|---|
| Preventive care, Nintendo's diagnostic table, connectors | Super Famicom Maintenance Guide |
| Fault-finding, test points, clocks and reset | Super Nintendo Troubleshooting Guide |
| Capacitors, by board revision | Super Famicom Capacitor Replacement Guide |
Before opening any Super Nintendo, switch it on with the adapter disconnected to discharge C67. This is Nintendo's own first disassembly instruction, and the reason it gives is that C67 discharges during maintenance and damages components.[1]
Documents hosted here: Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94), Nintendo Famicom Service Manual (which also covers the SHVC) and SNES Schematic.
Motherboard and schematic
[edit | edit source]-
SNS-CPU-RGB-01 mainboard -
PPU1 and PPU2 -
SNES schematic
Gallery
[edit | edit source]-
North American SNES -
Super Famicom (Japan) -
PAL SNES (Europe) -
SNES controller
Related pages
[edit | edit source]- Nintendo Entertainment System
- Nintendo 64
- Sega Mega Drive / Genesis (Model 1)
- List of Nintendo Hardware
References
[edit | edit source]- ↑ 1.00 1.01 1.02 1.03 1.04 1.05 1.06 1.07 1.08 1.09 1.10 1.11 1.12 1.13 Nintendo / Playtronic, Manual Técnico do Super NES, Rev. 01/94, hosted at Nintendo Super NES Technical Manual (Playtronic, Rev. 01-94). Console theory of operation (pp. 2-1 to 2-2): the AC adapter supplies 10 V DC unregulated; the on-board supply section comprises a noise filter, reverse-current protection, the power switch, a spike suppressor, a ripple filter and the regulator, and produces a regulated Vcc of 5 V and an unregulated Vs of 7 V used by the audio amplifier; the controller input section uses diode and capacitor arrays for surge protection and pull-up resistors, and the CPU samples the controllers about every 17 ms; the system timing section feeds a 21 MHz master clock to the CPU, PPU1, PPU2 and connector P1, and the CPU divides it by 6, 8 and 12 to give 3.58, 2.68 and 1.79 MHz, with DMA always at 2.68 MHz; the RESET section uses a 4 MHz oscillator, a 74HCU04 hex inverter, the CIC and the reset switch, and applies CIC reset to PPU2 first, then PPU1, then the CPU. Parts list: F1 a 1.5 A SSTR axial fuse, U12 a 7805, X1 a 21.453666 MHz (PAL-M) crystal, X2 a 4 MHz ceramic oscillator, and a 24.57 MHz ceramic oscillator. Adjustment and fault-finding: TC1 set to 21.453666 MHz; the 4 MHz CIC clock acceptable between 3.8 and 4.2 MHz. Disassembly: switch the console on with the AC adapter disconnected to discharge C67 before opening it. GPM section (pp. 3-1 ff.): the ground-plane mainboard removed the lower RF shield, shortened the PCB, deleted C67 and the 4 MHz oscillator, built the sound module circuit onto the mainboard, made TC1 a through-hole part, and removed the cartridge lock bar from the upper housing in favour of a warning label. IC handling notes (p. 8-2): do not measure ICs with a multimeter or signal tracer.
- ↑ 2.0 2.1 2.2 2.3 2.4 2.5 2.6 Nintendo, ファミコン・スーパーファミコン・ゲームボーイ サービスマニュアル (Famicom / Super Famicom / Game Boy Service Manual), issued 7 August 1992, hosted at Nintendo Famicom Service Manual. HVC section, pp. 2–10: AC adapter rated DC 10 V with a normal no-load output of DC 13.5 ± 1.5 V; HVC power-circuit block diagram showing a 7805 with 13–14 V in and 5 V out, drawn in both the standard and the VCCI variant; RF switch terminal carrying DC 5 V in game mode; the three solder points that need reinforcing around the DC jack; "before you decide it is a fault" table, p. 3; controller fault symptoms and the plug-in controller connectors, p. 4; exploded parts diagrams, pp. 7–9; Famicom repair price list, p. 10 (60-pin card connector, 15-pin D-sub jack, crystal, RF modulator unit, DC jack, 7805 three-terminal regulator, fuse listed for VCCI boards only, electret microphone, CMOS 4021 and 4069 in the controllers). SHVC section, pp. 11–15: power-switch harness polarity; SHVC power circuit, 7805 with 13–14 V in and 5 V out; Super Famicom repair price list (1.5 A SSTR axial fuse, 7805, 62-pin card connector in upper and lower halves, sound module).
- ↑ 3.0 3.1 3.2 Martin Korth, fullsnes — SNES hardware specifications — https://problemkaputt.de/fullsnes.htm , section "SNES Power Supply". NTSC and Japanese consoles take 10 V DC at 850 mA through a series diode, so the internal unregulated rail sits near 9 V; PAL consoles take 9 V AC and rectify it on board. A 7805 produces the only logic rail, +5 V, and the CPU, PPU and APU run solely from it; the unregulated rail feeds only the audio amplifier, and the console runs without it but silently. Also the source for the anti-eject lever fitted to the power switch of earlier consoles.